Message ID | 1401434911-26992-7-git-send-email-edgar.iglesias@gmail.com |
---|---|
State | New |
Headers | show |
Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 2 +- > target-arm/helper.c | 6 ++++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index f8ca1da..ef6a95d 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -187,7 +187,7 @@ typedef struct CPUARMState { > uint32_t ifsr_el2; /* Fault status registers. */ > uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > - uint64_t far_el[2]; /* Fault address registers. */ > + uint64_t far_el[4]; /* Fault address registers. */ Ahh my confusion from earlier is now clear. Perhaps the two commits should be merged? > uint64_t par_el1; /* Translation result. */ > uint32_t c9_insn; /* Cache lockdown registers. */ > uint32_t c9_data; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index da210b9..de5ee40 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1, > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, > + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > --- > > target-arm/cpu.h | 2 +- > > target-arm/helper.c | 6 ++++++ > > 2 files changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index f8ca1da..ef6a95d 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -187,7 +187,7 @@ typedef struct CPUARMState { > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > - uint64_t far_el[2]; /* Fault address registers. */ > > + uint64_t far_el[4]; /* Fault address registers. */ > > Ahh my confusion from earlier is now clear. Perhaps the two commits > should be merged? Hi, The point is to have a non-functional diff and then incrementally add the function to easy bisectability if something breaks. I don't have a very strong opinion though, so if people insist I can squash. Cheers, Edgar > > > uint64_t par_el1; /* Translation result. */ > > uint32_t c9_insn; /* Cache lockdown registers. */ > > uint32_t c9_data; > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index da210b9..de5ee40 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1, > > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > > + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1, > > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, > > + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, > > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, > > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, > > -- > Alex Bennée
On Wed, Jun 04, 2014 at 08:55:30AM +0100, Alex Benn�e wrote: > > Edgar E. Iglesias writes: > > > On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Benn?e wrote: > >> > >> Edgar E. Iglesias writes: > >> > >> > >> Ahh my confusion from earlier is now clear. Perhaps the two commits > >> should be merged? > > > > Hi, > > > > The point is to have a non-functional diff and then incrementally add > > the function to easy bisectability if something breaks. I don't > > have a very strong opinion though, so if people insist I can squash. > > Having each commit point be buildable and testable is certainly a > worthwhile goal from a bisect point of view. But for a simple no-op diff > (i.e. functionaly identical, just moving a few bits around) which will > then get updated with functional changes there is an argument to squash > the two together. I disagree. IMO when patches include refactoring + changes, the refactoring should be done with non functional changes (as far as possible) and then followed up with small easily reviewable functional patches. > > I like this patch series because the individual patches are narrow in > scope and not too big hence easier to review. I don't think squashing > some of non-function + functional diffs together detracts from that > nobel goal. As you say it's a judgement call.
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f8ca1da..ef6a95d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -187,7 +187,7 @@ typedef struct CPUARMState { uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el[2]; /* Fault address registers. */ + uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper.c b/target-arm/helper.c index da210b9..de5ee40 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,