[v1,05/16] target-arm: Add ESR_EL2 and 3

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/cpu.h    | 2 +-
 target-arm/helper.c | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

On 30 May 2014 02:28, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target-arm/cpu.h    | 2 +-
>  target-arm/helper.c | 8 ++++++++
>  2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 172a631..f8ca1da 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -185,7 +185,7 @@ typedef struct CPUARMState {
>          uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
>          uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
>          uint32_t ifsr_el2; /* Fault status registers.  */
> -        uint64_t esr_el[2];
> +        uint64_t esr_el[4];
>          uint32_t c6_region[8]; /* MPU base/size registers.  */
>          uint64_t far_el[2]; /* Fault address registers.  */
>          uint64_t par_el1;  /* Translation result. */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5350a99..da210b9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2116,6 +2116,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
>        .access = PL2_RW,
>        .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
> +    { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_NO_MIGRATE,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1,
>

Wouldn't opc2 be 0 for ESR_EL2?


> +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.esr_el[2]) },
>      { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
>        .type = ARM_CP_NO_MIGRATE,
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
> @@ -2134,6 +2138,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
>        .access = PL3_RW,
>        .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
> +    { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_NO_MIGRATE,
> +      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1,
>

Same with ESR_EL3, wouldn't it also have an opc2 value of 0?


> +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.esr_el[3]) },
>      { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
>        .type = ARM_CP_NO_MIGRATE,
>        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
> --
> 1.8.3.2
>
>

On Fri, May 30, 2014 at 09:12:52AM -0500, Greg Bellows wrote:
>    On 30 May 2014 02:28, Edgar E. Iglesias <[1]edgar.iglesias@gmail.com>
>    wrote:
> 
>      From: "Edgar E. Iglesias" <[2]edgar.iglesias@xilinx.com>
>      Signed-off-by: Edgar E. Iglesias <[3]edgar.iglesias@xilinx.com>
>      ---
>       target-arm/cpu.h    | 2 +-
>      Â target-arm/helper.c | 8 ++++++++
>      Â 2 files changed, 9 insertions(+), 1 deletion(-)
>      diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>      index 172a631..f8ca1da 100644
>      --- a/target-arm/cpu.h
>      +++ b/target-arm/cpu.h
>      @@ -185,7 +185,7 @@ typedef struct CPUARMState {
>      Â  Â  Â  Â  Â uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access
>      permissions */
>      Â  Â  Â  Â  Â uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access
>      permissions */
>      Â  Â  Â  Â  Â uint32_t ifsr_el2; /* Fault status registers. Â */
>      - Â  Â  Â  Â uint64_t esr_el[2];
>      + Â  Â  Â  Â uint64_t esr_el[4];
>      Â  Â  Â  Â  Â uint32_t c6_region[8]; /* MPU base/size registers.
>      Â */
>      Â  Â  Â  Â  Â uint64_t far_el[2]; /* Fault address registers. Â */
>      Â  Â  Â  Â  Â uint64_t par_el1; Â /* Translation result. */
>      diff --git a/target-arm/helper.c b/target-arm/helper.c
>      index 5350a99..da210b9 100644
>      --- a/target-arm/helper.c
>      +++ b/target-arm/helper.c
>      @@ -2116,6 +2116,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[]
>      = {
>      Â  Â  Â  Â .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
>      Â  Â  Â  Â .access = PL2_RW,
>      Â  Â  Â  Â .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
>      + Â  Â { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
>      + Â  Â  Â .type = ARM_CP_NO_MIGRATE,
>      + Â  Â  Â .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1,
> 
>    Wouldn't opc2 be 0 for ESR_EL2?
>    Â
> 
>      + Â  Â  Â .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
>      cp15.esr_el[2]) },
>      Â  Â  Â { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
>      Â  Â  Â  Â .type = ARM_CP_NO_MIGRATE,
>      Â  Â  Â  Â .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
>      @@ -2134,6 +2138,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[]
>      = {
>      Â  Â  Â  Â .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
>      Â  Â  Â  Â .access = PL3_RW,
>      Â  Â  Â  Â .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
>      + Â  Â { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
>      + Â  Â  Â .type = ARM_CP_NO_MIGRATE,
>      + Â  Â  Â .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1,
> 
>    Same with ESR_EL3, wouldn't it also have an opc2 value of 0?


Yes. I happened to have a fix for this in my tree but missed to
squash it in to these patches when preparing the series.

Fixed both for v2.

Cheers,
Edgar