From patchwork Fri May 30 07:28:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 353917 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3033D1400F5 for ; Fri, 30 May 2014 17:41:19 +1000 (EST) Received: from localhost ([::1]:51962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHRF-0002Mw-5b for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 03:41:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHQ9-0000vJ-Ly for qemu-devel@nongnu.org; Fri, 30 May 2014 03:40:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqHQ2-0007Lv-IA for qemu-devel@nongnu.org; Fri, 30 May 2014 03:40:09 -0400 Received: from mail-yk0-x22c.google.com ([2607:f8b0:4002:c07::22c]:50375) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHQ2-0007KQ-Dy for qemu-devel@nongnu.org; Fri, 30 May 2014 03:40:02 -0400 Received: by mail-yk0-f172.google.com with SMTP id 79so1209743ykr.17 for ; Fri, 30 May 2014 00:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y+LnPMcec90A/l/5VOkkddNct69nnM8CI6fphzruvoA=; b=qnafjrGhnSY1Dodx/w4vEYUE9sXEgppGg8p4x8udLl7WVDpPN8h9Ul5mzfkt/Dpytf o2jEcLi9ecQAiwS9Bfai4YDtVu9j3SYeDoiDRVdiNvpy5ZVGN2mbKF7EpDCouTyZie6Z 4BeJelati8+mjjF1YGbh36fyp6s5xWpwcH/BXADE5w8Zwyuk70yUPgu7lrXW5kfPjZIe oo/STSj6/x33An42hVnNS/iolu6V7PRr9m7U0Io0ixbqcSfYlS1pOPLRNmI762Py+B+i yNx+LiksZ0ateCRVZ/JmdEb0AHJb3BMC1dyywxzFK1K7m12GRFApal+HrdyR2F2/o2tb xRaA== X-Received: by 10.236.202.7 with SMTP id c7mr18211784yho.153.1401435601891; Fri, 30 May 2014 00:40:01 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id h34sm4845169yhm.52.2014.05.30.00.39.55 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 May 2014 00:40:01 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 May 2014 17:28:31 +1000 Message-Id: <1401434911-26992-17-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c07::22c Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v1 16/16] target-arm: Add support for VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 12 ++++++++++++ target-arm/cpu.c | 20 ++++++++++++++++++-- target-arm/cpu.h | 24 ++++++++++++++++++++++-- target-arm/helper-a64.c | 2 ++ target-arm/helper.c | 3 +++ target-arm/internals.h | 2 ++ 6 files changed, 59 insertions(+), 4 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index a579ffc..baf5643 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -498,6 +498,18 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); next_tb = 0; } + if (interrupt_request & CPU_INTERRUPT_VIRQ + && arm_excp_unmasked(cpu, EXCP_VIRQ)) { + cpu->exception_index = EXCP_VIRQ; + cc->do_interrupt(cpu); + next_tb = 0; + } + if (interrupt_request & CPU_INTERRUPT_VFIQ + && arm_excp_unmasked(cpu, EXCP_VFIQ)) { + cpu->exception_index = EXCP_VFIQ; + cc->do_interrupt(cpu); + next_tb = 0; + } #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 93bd6a0..f5f19e5 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -195,6 +195,20 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); } break; + case ARM_CPU_VIRQ: + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); + } + break; + case ARM_CPU_VFIQ: + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); + } + break; default: hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); } @@ -242,9 +256,11 @@ static void arm_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); + /* VIRQ and VFIQ are unused with KVM but we add them to maintain + the same interface as non-KVM CPUs. */ + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d15e8d2..17a1ddd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -53,6 +53,8 @@ #define EXCP_STREX 10 #define EXCP_HVC 11 /* HyperVisor Call */ #define EXCP_SMC 12 /* Secure Monitor Call */ +#define EXCP_VIRQ 13 +#define EXCP_VFIQ 14 #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 @@ -67,6 +69,8 @@ /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower @@ -85,6 +89,9 @@ /* Meanings of the ARMCPU object's two inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + typedef void ARMWriteCPFunc(void *opaque, int cp_info, int srcreg, int operand, uint32_t value); @@ -1135,6 +1142,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) unsigned int target_el = arm_excp_target_el(cs, excp_idx); /* FIXME: Use actual secure state. */ bool secure = false; + bool irq_unmasked = ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->daif & PSTATE_I)); /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1153,8 +1162,19 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) && (env->cp15.hcr_el2 & HCR_IMO)) { return true; } - return ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I)); + return irq_unmasked; + case EXCP_VFIQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_FMO)) { + /* VFIQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_IMO)) { + /* VIRQs are only taken when hypervized and non-secure. */ + return false; + } + return irq_unmasked; default: assert(0); break; diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 3894a6f..375759c 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -480,9 +480,11 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: + case EXCP_VIRQ: addr += 0x80; break; case EXCP_FIQ: + case EXCP_VFIQ: addr += 0x100; break; default: diff --git a/target-arm/helper.c b/target-arm/helper.c index 649476b..592b21f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3319,6 +3319,9 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) if (env->cp15.scr_el3 & SCR_FIQ) { target_el = 3; } + case EXCP_VIRQ: + case EXCP_VFIQ: + target_el = 1; break; } return target_el; diff --git a/target-arm/internals.h b/target-arm/internals.h index e50a68e..b1d2d4e 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -55,6 +55,8 @@ static const char * const excnames[] = { [EXCP_STREX] = "QEMU intercept of STREX", [EXCP_HVC] = "Hypervisor Call", [EXCP_SMC] = "Secure Monitor Call", + [EXCP_VIRQ] = "Virtual IRQ", + [EXCP_VFIQ] = "Virtual FIQ", }; static inline void arm_log_exception(int idx)