From patchwork Fri May 30 07:28:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 353909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CA18C14008A for ; Fri, 30 May 2014 17:36:22 +1000 (EST) Received: from localhost ([::1]:51918 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHMS-0003dC-PU for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 03:36:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHLY-0002Xb-8x for qemu-devel@nongnu.org; Fri, 30 May 2014 03:35:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqHLS-0005pc-9c for qemu-devel@nongnu.org; Fri, 30 May 2014 03:35:24 -0400 Received: from mail-pb0-x229.google.com ([2607:f8b0:400e:c01::229]:51936) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHLR-0005pS-Vs for qemu-devel@nongnu.org; Fri, 30 May 2014 03:35:18 -0400 Received: by mail-pb0-f41.google.com with SMTP id uo5so1434279pbc.14 for ; Fri, 30 May 2014 00:35:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=egb1KenyppFhe16xLSa2YDBTRF+FlHCR9FTlnjFVmgE=; b=PMvV8m1lCLM61iGjaaCqjpO/6wryFIN5ewQXzu50/tYCDdvCLJCpRgDAbpadVHcVPn ZICgtlAwKqtevOpqu2alEwyesBBJgKe9EkVQ/bdmohqBDjb2P85hWbASJ63huc3uUFjj +qEwLNcEq1bcKmepJha+nf2ZtSLvahEI95Jy6/yAdkuCU5/V0eQx/MBNi0PbpL1M7av5 zAaHZLFPqMBNHLR5MZhrQXZRCMyfcJCIoDL8OmUiWgG71Mk5yHui24unlMYzJyWW/MhM vvS/UP4iBfnqfZ4CL8nSru5ZeVps03HQiT/kTMFlS5AapKhYYfKc61RGSdkUpF3rgNYW TgCg== X-Received: by 10.68.129.99 with SMTP id nv3mr15737882pbb.128.1401435316932; Fri, 30 May 2014 00:35:16 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id zq5sm4825167pbb.37.2014.05.30.00.35.10 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 May 2014 00:35:16 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 May 2014 17:28:24 +1000 Message-Id: <1401434911-26992-10-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::229 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v1 09/16] target-arm: A64: Refactor aarch64_cpu_do_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Introduce new_el and new_mode in preparation for future patches that add support for taking exceptions to and from EL2 and 3. No functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 11 +++++++++++ target-arm/helper-a64.c | 24 +++++++++++++----------- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 28521d4..5c74adc 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -461,6 +461,12 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 +/* Map EL and handler into a PSTATE_MODE. */ +static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) +{ + return (el << 2) | handler; +} + /* Return the current PSTATE value. For the moment we don't support 32<->64 bit * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. @@ -709,6 +715,11 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) } void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); +static inline unsigned int arm_excp_target_el(CPUState *cs, + unsigned int excp_idx) +{ + return 1; +} /* Interface between CPU and Interrupt controller. */ void armv7m_nvic_set_pending(void *opaque, int irq); diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index d647441..7d94a74 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -443,10 +443,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong addr = env->cp15.vbar_el[1]; + unsigned int new_el = arm_excp_target_el(cs, cs->exception_index); + target_ulong addr = env->cp15.vbar_el[new_el]; + unsigned int new_mode = aarch64_pstate_mode(new_el, true); int i; - if (arm_current_pl(env) == 0) { + if (arm_current_pl(env) < new_el) { if (env->aarch64) { addr += 0x400; } else { @@ -464,14 +466,14 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - env->cp15.esr_el[1] = env->exception.syndrome; - env->cp15.far_el[1] = env->exception.vaddress; + env->cp15.esr_el[new_el] = env->exception.syndrome; + env->cp15.far_el[new_el] = env->exception.vaddress; switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[1]); + env->cp15.far_el[new_el]); break; case EXCP_BKPT: case EXCP_UDEF: @@ -488,15 +490,15 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env); + env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); aarch64_save_sp(env, arm_current_pl(env)); - env->elr_el[1] = env->pc; + env->elr_el[new_el] = env->pc; } else { env->banked_spsr[0] = cpsr_read(env); if (!env->thumb) { - env->cp15.esr_el[1] |= 1 << 25; + env->cp15.esr_el[new_el] |= 1 << 25; } - env->elr_el[1] = env->regs[15]; + env->elr_el[new_el] = env->regs[15]; for (i = 0; i < 15; i++) { env->xregs[i] = env->regs[i]; @@ -505,9 +507,9 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->condexec_bits = 0; } - pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h); + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; - aarch64_restore_sp(env, 1); + aarch64_restore_sp(env, new_el); env->pc = addr; cs->interrupt_request |= CPU_INTERRUPT_EXITTB;