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[v5,18/23] target-arm: A64: Trap ERET from EL0 at translation time

Message ID 1400980132-25949-19-git-send-email-edgar.iglesias@gmail.com
State New
Headers show

Commit Message

Edgar E. Iglesias May 25, 2014, 1:08 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/translate-a64.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bfd139a..ec6a39d 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1507,6 +1507,10 @@  static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
         break;
     case 4: /* ERET */
+        if (s->current_pl == 0) {
+            unallocated_encoding(s);
+            return;
+        }
         gen_helper_exception_return(cpu_env);
         s->is_jmp = DISAS_JUMP;
         return;