From patchwork Sun May 25 01:08:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 352206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CA608140083 for ; Sun, 25 May 2014 11:21:13 +1000 (EST) Received: from localhost ([::1]:49931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN7f-0002cq-GD for incoming@patchwork.ozlabs.org; Sat, 24 May 2014 21:21:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN72-0001xq-Nh for qemu-devel@nongnu.org; Sat, 24 May 2014 21:20:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoN6w-0007AL-3q for qemu-devel@nongnu.org; Sat, 24 May 2014 21:20:32 -0400 Received: from mail-wi0-x232.google.com ([2a00:1450:400c:c05::232]:54563) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN6v-0007AF-Sz for qemu-devel@nongnu.org; Sat, 24 May 2014 21:20:26 -0400 Received: by mail-wi0-f178.google.com with SMTP id cc10so2614930wib.5 for ; Sat, 24 May 2014 18:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=As2Fun8Wf4cwk0kEQOw6h9gxRxuz7u7nutC3aI4oUyA=; b=WiLomwQZaZo7IuqcixDMgt9+45Jx0BIvm2znxZTO4MUN7DZxKJjISEp6n6mP2SNDjg jkL3J+pYBanBfT+9j16WsDGYSFx+iNCuEoCLTUMneACTt64sP2uePy4YI3CgIarvvarS Da1WgVGHYxQnj0ChA+TMBcYYeeCe3BDNNxc3yOgPrrUbxtAigbSl0hESnVOLOVwAVg/7 xGqPTKyLH1LyJd6p8+g+cc1UcZqy4lvdYiDwVKDzZq9IDcCdVMsOaxV3hYCvSAJueWWt 35GoTUjEUgjPy7RJPDNyXnTXqwwitrMFOj41FbHXACvtm5ZEubgpqVBGPTgpncPT6Z// vNnw== X-Received: by 10.180.79.9 with SMTP id f9mr738718wix.52.1400980825141; Sat, 24 May 2014 18:20:25 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id g9sm14498292wja.39.2014.05.24.18.20.19 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 24 May 2014 18:20:24 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 25 May 2014 11:08:45 +1000 Message-Id: <1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> References: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c05::232 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, greg.bellows@linaro.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v5 16/23] target-arm: Register EL3 versions of ELR and SPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 81de010..cb7c964a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2090,6 +2090,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2344,6 +2357,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new * PMSA core later than the ARM946 will require that we