From patchwork Sun May 25 01:08:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 352205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 79063140083 for ; Sun, 25 May 2014 11:20:20 +1000 (EST) Received: from localhost ([::1]:49925 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN6o-0001bG-Dx for incoming@patchwork.ozlabs.org; Sat, 24 May 2014 21:20:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN6O-0000j6-5p for qemu-devel@nongnu.org; Sat, 24 May 2014 21:19:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoN6I-0006jL-6t for qemu-devel@nongnu.org; Sat, 24 May 2014 21:19:52 -0400 Received: from mail-we0-x233.google.com ([2a00:1450:400c:c03::233]:38658) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN6I-0006hu-0g for qemu-devel@nongnu.org; Sat, 24 May 2014 21:19:46 -0400 Received: by mail-we0-f179.google.com with SMTP id q59so6326246wes.24 for ; Sat, 24 May 2014 18:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lmM+pLctFctmUsSUN1M0h6OpKDkYjBTE60p1qXHjBao=; b=pWm7wK1TXEGPF25w/qMaOa+bu59KDfTwtxow5LQnfgmw6ny6LLb8E7/PdPAPsSzqlI iKfJjgG5o4J9o+G2Rt83q+0fbHzY6HMdNaFwYRuMoZzMn8/9We0L41T13qWr6TRQGKgt OnaVzITydlD9P+R/uVd4zysWuddw3qMIZ+JJfgD6SECE482AY43Uw0g33XGwHV9DPYd7 g1age7Qjp4sv9o0QVubIElf0phvsz/2OjtPN5trVegD0isXzkISTFUFGx+7u+qic9eNJ E34qDH06yij7FRJb2wS0AhCxPrLKw+vtyUXfGlZmGmoMJpIpeC9PT01aurWHv1Kyba5P eYAA== X-Received: by 10.180.82.99 with SMTP id h3mr2323954wiy.25.1400980785257; Sat, 24 May 2014 18:19:45 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id wo9sm14488824wjb.48.2014.05.24.18.19.39 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 24 May 2014 18:19:44 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 25 May 2014 11:08:44 +1000 Message-Id: <1400980132-25949-16-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> References: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c03::233 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, greg.bellows@linaro.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5e2eac3..81de010 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2077,6 +2077,19 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el2_cp_reginfo[] = { + { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, + { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2328,6 +2341,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_cp_reginfo); define_aarch64_debug_regs(cpu); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_arm_cp_regs(cpu, v8_el2_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new * PMSA core later than the ARM946 will require that we