From patchwork Sun May 25 01:08:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 352201 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5AA88140091 for ; Sun, 25 May 2014 11:17:48 +1000 (EST) Received: from localhost ([::1]:49901 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN4M-00060c-83 for incoming@patchwork.ozlabs.org; Sat, 24 May 2014 21:17:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN3o-0004xl-2c for qemu-devel@nongnu.org; Sat, 24 May 2014 21:17:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoN3i-00065D-3s for qemu-devel@nongnu.org; Sat, 24 May 2014 21:17:12 -0400 Received: from mail-we0-x22a.google.com ([2a00:1450:400c:c03::22a]:47311) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoN3h-000658-UJ for qemu-devel@nongnu.org; Sat, 24 May 2014 21:17:06 -0400 Received: by mail-we0-f170.google.com with SMTP id u57so6635307wes.1 for ; Sat, 24 May 2014 18:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LO4+IgfIUP7T7fmegudbvb3WnEpYFE72LkG+hm9Myp4=; b=KaI/rLapFQv4a5cCGSPuRu7Dtky0gnkIWjGj654YVVuCPlL4plp8KUknB9RymAYnB2 YPH3G7AZD8XT8j9xNBiYlsRQWTFrcaHwQ2ZU4kpkOYA/x/19nyDTDT3Eu0rAcr0Rl5kt 1uWPMLZk6hUs+b5lRuQ4XsvMJuKCUvBPlp1wQmN85QFew2aCvT6Z62yMLUrfePxaNiAd QqSuJwwEISDI4IyVLvKtWB8JzumuqIwzQA1IFR9rMBHKrUmhcCFmThXno6OOf04lgIiI jJaOlt9K3q208SWvYw1QwraPCNHYFFNuyc2gYHJthF0glex6tFIHREuY7yxv7+CekFAS r5Vw== X-Received: by 10.194.91.144 with SMTP id ce16mr15748760wjb.18.1400980625167; Sat, 24 May 2014 18:17:05 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id oy4sm5473166wjb.41.2014.05.24.18.16.59 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 24 May 2014 18:17:04 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 25 May 2014 11:08:40 +1000 Message-Id: <1400980132-25949-12-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> References: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c03::22a Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, greg.bellows@linaro.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v5 11/23] target-arm: Add SPSR entries for EL2/HYP and EL3/MON X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 4 +++- target-arm/helper.c | 4 ++++ target-arm/machine.c | 6 +++--- target-arm/translate.c | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 60414ac..5919dfd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -143,7 +143,7 @@ typedef struct CPUARMState { uint32_t spsr; /* Banked registers. */ - uint64_t banked_spsr[6]; + uint64_t banked_spsr[8]; uint32_t banked_r13[6]; uint32_t banked_r14[6]; @@ -563,7 +563,9 @@ enum arm_cpu_mode { ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_SVC = 0x13, + ARM_CPU_MODE_MON = 0x16, ARM_CPU_MODE_ABT = 0x17, + ARM_CPU_MODE_HYP = 0x1a, ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_SYS = 0x1f }; diff --git a/target-arm/helper.c b/target-arm/helper.c index bba7297..5e2eac3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3084,6 +3084,10 @@ int bank_number(int mode) return 4; case ARM_CPU_MODE_FIQ: return 5; + case ARM_CPU_MODE_HYP: + return 6; + case ARM_CPU_MODE_MON: + return 7; } hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 233e70d..3bcc7cc 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 19, - .minimum_version_id = 19, + .version_id = 20, + .minimum_version_id = 20, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -233,7 +233,7 @@ const VMStateDescription vmstate_arm_cpu = { .offset = 0, }, VMSTATE_UINT32(env.spsr, ARMCPU), - VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), + VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), diff --git a/target-arm/translate.c b/target-arm/translate.c index 08732a0..c2dfbfe 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11052,8 +11052,8 @@ void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) } static const char *cpu_mode_names[16] = { - "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", - "???", "???", "???", "und", "???", "???", "???", "sys" + "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", + "???", "???", "hyp", "und", "???", "???", "???", "sys" }; void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,