From patchwork Fri May 23 00:41:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 351670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 298CC140082 for ; Fri, 23 May 2014 10:44:55 +1000 (EST) Received: from localhost ([::1]:40247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WndbR-0001an-6N for incoming@patchwork.ozlabs.org; Thu, 22 May 2014 20:44:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndb2-00013W-6W for qemu-devel@nongnu.org; Thu, 22 May 2014 20:44:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wndaw-0005Vg-7R for qemu-devel@nongnu.org; Thu, 22 May 2014 20:44:28 -0400 Received: from mail-qc0-x22e.google.com ([2607:f8b0:400d:c01::22e]:35509) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndaw-0005Vb-2P for qemu-devel@nongnu.org; Thu, 22 May 2014 20:44:22 -0400 Received: by mail-qc0-f174.google.com with SMTP id x13so6793459qcv.19 for ; Thu, 22 May 2014 17:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VXVZqNhHC9Keay6mRGJHU977N64avbtLHASgDFO+HHY=; b=zF+5+/84uG22Li+UsO+sLAHazvOSy7lyBuRgVY88Ts0kINwX0w6J2ZBToh4hUyGVZ/ 1I2jN4g7Z8GqF64XwH0lxeq+Khqq46VFQblGEyesGs4T0KH6CuPO/0ciXKxG7EfemYKh fFWSdT6p8u4tFSoE+FXFFouazchjZsgHA63llQYpn/3rD9T+kLbnxS1DlYXAjMI0yaZa DifoFiO2o1EiXWeBZq6EAqqZjRcYysEtg5u6RjyAs5faXAgQ709JChJmASLRHKjHDEqA VVzl0lC2pd2LVzm9hgtVDcOMEy2W2cMMS9Y4/xNTpqD7YB3ZfarGAL7tjNPq4bEqFe6X WSNQ== X-Received: by 10.224.87.132 with SMTP id w4mr1512646qal.89.1400805861659; Thu, 22 May 2014 17:44:21 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id c16sm2274827qaw.4.2014.05.22.17.44.15 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 17:44:20 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 23 May 2014 10:41:59 +1000 Message-Id: <1400805738-11889-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22e Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 02/21] target-arm: Make esr_el1 an array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" No functional change. Prepares for future addtion of EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/helper-a64.c | 4 ++-- target-arm/helper.c | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 19013ad..0b30ab8 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -185,7 +185,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint32_t ifsr_el2; /* Fault status registers. */ - uint64_t esr_el1; + uint64_t esr_el[2]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el1; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 7e5073b..13c5865 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -464,7 +464,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - env->cp15.esr_el1 = env->exception.syndrome; + env->cp15.esr_el[1] = env->exception.syndrome; env->cp15.far_el1 = env->exception.vaddress; switch (cs->exception_index) { @@ -495,7 +495,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } else { env->banked_spsr[0] = cpsr_read(env); if (!env->thumb) { - env->cp15.esr_el1 |= 1 << 25; + env->cp15.esr_el[1] |= 1 << 25; } env->elr_el[1] = env->regs[15]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 6d6601e..107cd5f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1452,7 +1452,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, @@ -1460,7 +1460,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, }, + .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), @@ -1521,7 +1521,7 @@ static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo omap_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, @@ -3338,11 +3338,11 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; case EXCP_DATA_ABORT: - env->cp15.esr_el1 = env->exception.fsr; + env->cp15.esr_el[1] = env->exception.fsr; env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - (uint32_t)env->cp15.esr_el1, + (uint32_t)env->cp15.esr_el[1], (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x10;