From patchwork Fri May 23 00:42:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 351682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BD95D140086 for ; Fri, 23 May 2014 10:53:31 +1000 (EST) Received: from localhost ([::1]:40323 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndjl-0004pM-GT for incoming@patchwork.ozlabs.org; Thu, 22 May 2014 20:53:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndj4-0003gf-3a for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wndiw-0008Bb-PT for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:46 -0400 Received: from mail-pb0-x230.google.com ([2607:f8b0:400e:c01::230]:58443) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndiw-0008BJ-GX for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:38 -0400 Received: by mail-pb0-f48.google.com with SMTP id rr13so3268175pbb.7 for ; Thu, 22 May 2014 17:52:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=As2Fun8Wf4cwk0kEQOw6h9gxRxuz7u7nutC3aI4oUyA=; b=DV4n0FzkrxFxsTSqarOSk+ruae3ZX/eTyWoPOHJmyG+PpSi5CTD4IMib6AavetACng AdWBM4ZM4Vr0eHDQjxbdoxQFQ/Zs+Y+iau10jxiwYONfurds3EqHMnOmx7JEQlUimYg3 3Z5P7cjMqe9PU6fIBVDylUw2wiootKjgeCRkVriL2O5SxJ71I3tyjSCjJlDQT0NSjYEF oSxtPa7YGa+Qs9WRcM3+brgyj0j/1DAU3BG5J2Kn4a3g8UWNX21L1+3/89L+zqAsqP6/ E5Lin3uQhwr7vDrtNXguNWwkI33uFTEMGRw9EcOiNpqkoYJJ1KrP8oQpQ6Hqyx8Ko9o2 mxKw== X-Received: by 10.68.164.229 with SMTP id yt5mr1585022pbb.28.1400806357353; Thu, 22 May 2014 17:52:37 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id vg1sm1592833pbc.44.2014.05.22.17.52.30 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 17:52:36 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 23 May 2014 10:42:11 +1000 Message-Id: <1400805738-11889-15-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::230 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 14/21] target-arm: Register EL3 versions of ELR and SPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 81de010..cb7c964a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2090,6 +2090,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2344,6 +2357,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new * PMSA core later than the ARM946 will require that we