| Message ID | 1399356506-5609-10-git-send-email-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Tue, May 06, 2014 at 04:08:13PM +1000, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> Noticed I missed updating cpu_mode_names[] Queued an update to translate.c for v2. Cheers, Edgar > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 4 +++- > target-arm/helper.c | 4 ++++ > target-arm/machine.c | 8 ++++---- > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index fd8ce70..6e6625b 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -143,7 +143,7 @@ typedef struct CPUARMState { > uint32_t spsr; > > /* Banked registers. */ > - uint64_t banked_spsr[6]; > + uint64_t banked_spsr[8]; > uint32_t banked_r13[6]; > uint32_t banked_r14[6]; > > @@ -566,7 +566,9 @@ enum arm_cpu_mode { > ARM_CPU_MODE_FIQ = 0x11, > ARM_CPU_MODE_IRQ = 0x12, > ARM_CPU_MODE_SVC = 0x13, > + ARM_CPU_MODE_MON = 0x16, > ARM_CPU_MODE_ABT = 0x17, > + ARM_CPU_MODE_HYP = 0x1a, > ARM_CPU_MODE_UND = 0x1b, > ARM_CPU_MODE_SYS = 0x1f > }; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index baeaa28..ba1830d 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3078,6 +3078,10 @@ int bank_number(int mode) > return 4; > case ARM_CPU_MODE_FIQ: > return 5; > + case ARM_CPU_MODE_HYP: > + return 6; > + case ARM_CPU_MODE_MON: > + return 7; > } > hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); > } > diff --git a/target-arm/machine.c b/target-arm/machine.c > index 92ac621..e95be47 100644 > --- a/target-arm/machine.c > +++ b/target-arm/machine.c > @@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id) > > const VMStateDescription vmstate_arm_cpu = { > .name = "cpu", > - .version_id = 19, > - .minimum_version_id = 19, > - .minimum_version_id_old = 19, > + .version_id = 20, > + .minimum_version_id = 20, > + .minimum_version_id_old = 20, > .pre_save = cpu_pre_save, > .post_load = cpu_post_load, > .fields = (VMStateField[]) { > @@ -238,7 +238,7 @@ const VMStateDescription vmstate_arm_cpu = { > .offset = 0, > }, > VMSTATE_UINT32(env.spsr, ARMCPU), > - VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), > + VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), > VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), > VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), > VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), > -- > 1.8.3.2 >
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index fd8ce70..6e6625b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -143,7 +143,7 @@ typedef struct CPUARMState { uint32_t spsr; /* Banked registers. */ - uint64_t banked_spsr[6]; + uint64_t banked_spsr[8]; uint32_t banked_r13[6]; uint32_t banked_r14[6]; @@ -566,7 +566,9 @@ enum arm_cpu_mode { ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_SVC = 0x13, + ARM_CPU_MODE_MON = 0x16, ARM_CPU_MODE_ABT = 0x17, + ARM_CPU_MODE_HYP = 0x1a, ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_SYS = 0x1f }; diff --git a/target-arm/helper.c b/target-arm/helper.c index baeaa28..ba1830d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3078,6 +3078,10 @@ int bank_number(int mode) return 4; case ARM_CPU_MODE_FIQ: return 5; + case ARM_CPU_MODE_HYP: + return 6; + case ARM_CPU_MODE_MON: + return 7; } hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 92ac621..e95be47 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 19, - .minimum_version_id = 19, - .minimum_version_id_old = 19, + .version_id = 20, + .minimum_version_id = 20, + .minimum_version_id_old = 20, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -238,7 +238,7 @@ const VMStateDescription vmstate_arm_cpu = { .offset = 0, }, VMSTATE_UINT32(env.spsr, ARMCPU), - VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), + VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),