From patchwork Thu Jul 14 09:41:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsuneo Saito X-Patchwork-Id: 104658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id ABAA2B6F69 for ; Thu, 14 Jul 2011 20:14:40 +1000 (EST) Received: from localhost ([::1]:38628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIwG-0000Ts-Uy for incoming@patchwork.ozlabs.org; Thu, 14 Jul 2011 06:14:37 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIR1-0001D0-Jg for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:42:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QhIQz-0002ul-D6 for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:42:19 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:50651) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIQy-0002t2-RE for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:42:17 -0400 Received: by mail-iy0-f173.google.com with SMTP id 3so56035iyb.4 for ; Thu, 14 Jul 2011 02:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Lq45MIWhVdQ6mVnOII0l37Zij/OAbeyTkhpnW7WJaPE=; b=emglGa/muVSlfBt5qZFiIWgeAcun/xAPPqqs4l+qDzelM9bPhj1j7gpLGeJ+FIgmEb JvRd2+YQN4avmwjFbhOQhZdid+gvydOTG5jVvusxQCnac5ckk5+oojSWZfNY8M2iszrW tZwX3FQq6adHSGcsY+9b0Glu4zjU6od+1+ris= Received: by 10.42.158.138 with SMTP id h10mr2172796icx.157.1310636536557; Thu, 14 Jul 2011 02:42:16 -0700 (PDT) Received: from localhost.localdomain (tetkyo149119.tkyo.te.ftth2.ppp.infoweb.ne.jp [202.219.195.119]) by mx.google.com with ESMTPS id hq1sm92469icc.2.2011.07.14.02.42.14 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Jul 2011 02:42:15 -0700 (PDT) From: Tsuneo Saito To: qemu-devel@nongnu.org Date: Thu, 14 Jul 2011 18:41:38 +0900 Message-Id: <1310636503-8956-4-git-send-email-tsnsaito@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1310636503-8956-1-git-send-email-tsnsaito@gmail.com> References: <1310636503-8956-1-git-send-email-tsnsaito@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.173 Cc: Tsuneo Saito Subject: [Qemu-devel] [PATCH v2 3/8] SPARC64: Implement stfa/stdfa/stqfa instrcutions properly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements sparcv9 stfa/stdfa/stqfa instructions with non block-store ASIs. Signed-off-by: Tsuneo Saito --- target-sparc/op_helper.c | 15 +++++++++++---- target-sparc/translate.c | 2 -- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index a75ac4f..fe71829 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -3396,6 +3396,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) { unsigned int i; target_ulong val = 0; + CPU_DoubleU u; helper_check_align(addr, 3); addr = asi_address_mask(env, asi, addr); @@ -3440,16 +3441,22 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) switch(size) { default: case 4: - val = *((uint32_t *)&env->fpr[rd]); + helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size); break; case 8: - val = *((int64_t *)&DT0); + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr, u.ll, asi, size); break; case 16: - // XXX + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr, u.ll, asi, 8); + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr + 8, u.ll, asi, 8); break; } - helper_st_asi(addr, val, asi, size); } target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 1e7e68d..a5a8eaf 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4742,12 +4742,10 @@ static void disas_sparc_insn(DisasContext * dc) r_const = tcg_const_i32(7); gen_helper_check_align(cpu_addr, r_const); tcg_temp_free_i32(r_const); - gen_op_load_fpr_QT0(QFPREG(rd)); gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); } break; case 0x37: /* V9 stdfa */ - gen_op_load_fpr_DT0(DFPREG(rd)); gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; case 0x3c: /* V9 casa */