From patchwork Wed Mar 30 12:56:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 1611121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=greensocs.com header.i=@greensocs.com header.a=rsa-sha256 header.s=mail header.b=bMijghb3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KT67l2Lcxz9sFk for ; Thu, 31 Mar 2022 00:03:47 +1100 (AEDT) Received: from localhost ([::1]:51572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZXzF-0006E3-24 for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2022 09:03:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXsZ-0006l8-M2; Wed, 30 Mar 2022 08:56:52 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40866) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXsX-0004Y8-GF; Wed, 30 Mar 2022 08:56:51 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id 09B3621C38; Wed, 30 Mar 2022 12:56:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1648645004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=CTHLxshGLn+LMFCmOT0tST5SI/piv8b6mpuMZAFlww0=; b=bMijghb3ZxySJFZ5hguLZ1NJj61rRhufZGQ0OOc662vJmtougXTMoULm4QbNncYwsTKjWj 5TohKjSz6kck9gbHVue+ljKHpJBNGPk4pA2rrNs7mAqxIqU0M661O+3kDeFI6Pwu8EVmBU gNy56SQsG4mfwNpvyur3TEXUrkZclRQ= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [RFC PATCH 00/18] user-creatable cpu clusters Date: Wed, 30 Mar 2022 14:56:21 +0200 Message-Id: <20220330125639.201937-1-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam: Yes Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , Bin Meng , qemu-riscv@nongnu.org, Alistair Francis , mark.burton@greensocs.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , qemu-arm@nongnu.org, Palmer Dabbelt , Vijai Kumar K , "Edgar E. Iglesias" , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Hi, This series add devices to be able to user-create (coldplug) cpu clusters. The existing cpu cluster dictates how cpus are exposed in gdb, but it does not handle the cpu objects creation. This series adds a new device to handle both issues and adds support for two architectures: arm and riscv. Please look at patches 2 and 3 for more details about the new device. Last part concerning the riscv is rfc as I do non-backward compatible updates. I'm not sure what migration (or other) constraints we have on these machines and I probably need to make some changes to cope with them. This series almost deprecates the cpu-cluster type as all uses but one are replaced. It is organized as follows: + Patches 1 to 7 adds a new base device to replace cpu-cluster + Patches 8 and 9 adds an arm specific version and replace existing clusters in the xlnx-zynqmp machine. + patches 10 to 17 updates the riscv_array. It was already used to create cpus but was not a cpu cluster. Thanks for any comments, --- Damien Damien Hedde (18): define MAX_CLUSTERS in cpu.h instead of cluster.h hw/cpu/cpus: introduce _cpus_ device hw/cpu/cpus: prepare to handle cpu clusters hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_ gdbstub: deal with _cpus_ object instead of _cpu-cluster_ hw/cpu/cluster: remove cluster_id now that gdbstub is updated hw/cpu/cpus: add a common start-powered-off property hw/arm/arm_cpus: add arm_cpus device hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus hw/riscv/riscv_hart: prepare transition to cpus hw/riscv: prepare riscv_hart transition to cpus hw/riscv/virt: prepare riscv_hart transition to cpus hw/riscv/spike: prepare riscv_hart transition to cpus hw/riscv/riscv_hart: use cpus as base class hw/riscv/sifive_uµchip_pfsoc: apply riscv_hart_array update hw/riscv: update remaining machines due to riscv_hart_array update hw/riscv/riscv_hart: remove temporary features add myself as reviewer of the newly added _cpus_ include/hw/arm/arm_cpus.h | 45 +++++++ include/hw/arm/xlnx-zynqmp.h | 8 +- include/hw/core/cpu.h | 6 + include/hw/cpu/cluster.h | 26 ++-- include/hw/cpu/cpus.h | 93 ++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 2 - include/hw/riscv/riscv_hart.h | 25 +++- include/hw/riscv/sifive_u.h | 2 - gdbstub.c | 12 +- hw/arm/arm_cpus.c | 63 ++++++++++ hw/arm/xlnx-zynqmp.c | 121 +++++++----------- hw/cpu/cluster.c | 53 ++++---- hw/cpu/cpus.c | 195 +++++++++++++++++++++++++++++ hw/riscv/boot.c | 2 +- hw/riscv/microchip_pfsoc.c | 28 +---- hw/riscv/opentitan.c | 4 +- hw/riscv/riscv_hart.c | 44 ++----- hw/riscv/shakti_c.c | 4 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 31 ++--- hw/riscv/spike.c | 18 +-- hw/riscv/virt.c | 79 +++++++----- MAINTAINERS | 3 + hw/arm/meson.build | 1 + hw/cpu/meson.build | 2 +- 25 files changed, 612 insertions(+), 259 deletions(-) create mode 100644 include/hw/arm/arm_cpus.h create mode 100644 include/hw/cpu/cpus.h create mode 100644 hw/arm/arm_cpus.c create mode 100644 hw/cpu/cpus.c