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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id w35sm3433795lfu.273.2022.01.30.15.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:07 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Date: Mon, 31 Jan 2022 00:12:00 +0100 Message-Id: <20220130231206.34035-1-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::136 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" This adds the necessary modeling to support some of our firmware tests at EL3 implementing PSCI (TBM). These are the test-cases that were previously relying on QEMU's builtin PSCI emulation. I've only tested this on top of Peter's recent PSCI emulation fixes. Cheers, Edgar Edgar E. Iglesias (6): hw/arm/xlnx-zynqmp: Add unimplemented SERDES area target/arm: Make rvbar settable after realize hw/misc: Add a model of the Xilinx ZynqMP CRF hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF hw/misc: Add a model of the Xilinx ZynqMP APU Control hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control include/hw/arm/xlnx-zynqmp.h | 4 + include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++ include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 45 ++++- hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++ hw/misc/xlnx-zynqmp-crf.c | 270 +++++++++++++++++++++++++ target/arm/cpu.c | 7 +- hw/misc/meson.build | 2 + 8 files changed, 879 insertions(+), 6 deletions(-) create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c create mode 100644 hw/misc/xlnx-zynqmp-crf.c