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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b65sm39371533pfg.209.2022.01.03.22.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 22:34:47 -0800 (PST) From: Jim Shu To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware Date: Tue, 4 Jan 2022 14:34:06 +0800 Message-Id: <20220104063408.658169-1-jim.shu@sifive.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f34 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f34; envelope-from=jim.shu@sifive.com; helo=mail-qv1-xf34.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jim Shu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit register, but QEMU emulation supports low part access now. Enhance QEMU emulation to support high 32-bit access. Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit accesses of PDMA registers are supported. Changelog: v2: * Fix high 32-bit write access of 64-bit RO registers * Fix commit log Jim Shu (2): hw/dma: sifive_pdma: support high 32-bit access of 64-bit register hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers hw/dma/sifive_pdma.c | 181 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 159 insertions(+), 22 deletions(-)