[0/2] Align SiFive PDMA behavior to real hardware

Message ID	20211228005236.415583-1-jim.shu@sifive.com
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Jim Shu <jim.shu@sifive.com> To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/2] Align SiFive PDMA behavior to real hardware Date: Tue, 28 Dec 2021 08:52:34 +0800 Message-Id: <20211228005236.415583-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Jim Shu <jim.shu@sifive.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Align SiFive PDMA behavior to real hardware \| expand [0/2] Align SiFive PDMA behavior to real hardware [1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register [2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

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20211228005236.415583-1-jim.shu@sifive.com

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From: Jim Shu <jim.shu@sifive.com>
To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com,
 frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 0/2] Align SiFive PDMA behavior to real hardware
Date: Tue, 28 Dec 2021 08:52:34 +0800
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Series

Align SiFive PDMA behavior to real hardware | expand

Message

Jim Shu Dec. 28, 2021, 12:52 a.m. UTC

HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation support low part access now. Enhance QEMU
emulation to support high 32-bit access. 

Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.

Jim Shu (2):
  hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
  hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

 hw/dma/sifive_pdma.c | 178 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 156 insertions(+), 22 deletions(-)