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Thu, 06 Sep 2018 23:40:55 -0700 (PDT) Received: from rashmica.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y69-v6sm14958108pfd.36.2018.09.06.23.40.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Sep 2018 23:40:54 -0700 (PDT) From: Rashmica Gupta To: pdbg@lists.ozlabs.org Date: Fri, 7 Sep 2018 16:40:02 +1000 Message-Id: <20180907064015.1058-4-rashmica.g@gmail.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180907064015.1058-1-rashmica.g@gmail.com> References: <20180907064015.1058-1-rashmica.g@gmail.com> Subject: [Pdbg] [PATCH v2 03/16] libpdbg: Print the name of the instruction when erroring X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: npiggin@gmail.com MIME-Version: 1.0 Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Rashmica Gupta --- libpdbg/chip.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/libpdbg/chip.c b/libpdbg/chip.c index 80a2261..1c5080e 100644 --- a/libpdbg/chip.c +++ b/libpdbg/chip.c @@ -29,7 +29,7 @@ static uint64_t mfspr(uint64_t reg, uint64_t spr) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mfspr\n"); return MFSPR_OPCODE | (reg << 21) | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6); } @@ -37,7 +37,7 @@ static uint64_t mfspr(uint64_t reg, uint64_t spr) static uint64_t mtspr(uint64_t spr, uint64_t reg) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mtspr\n"); return MTSPR_OPCODE | (reg << 21) | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6); } @@ -45,9 +45,9 @@ static uint64_t mtspr(uint64_t spr, uint64_t reg) static uint64_t mfocrf(uint64_t reg, uint64_t cr) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mfocrf\n"); if (cr > 7) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid CR field specified\n"); return MFOCRF_OPCODE | (reg << 21) | (1U << (12 + cr)); } @@ -55,7 +55,7 @@ static uint64_t mfocrf(uint64_t reg, uint64_t cr) static uint64_t mfnia(uint64_t reg) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mfnia\n"); return MFNIA_OPCODE | (reg << 21); } @@ -63,7 +63,7 @@ static uint64_t mfnia(uint64_t reg) static uint64_t mtnia(uint64_t reg) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mtnia\n"); return MTNIA_OPCODE | (reg << 21); } @@ -71,7 +71,7 @@ static uint64_t mtnia(uint64_t reg) static uint64_t mfmsr(uint64_t reg) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mfmsr\n"); return MFMSR_OPCODE | (reg << 21); } @@ -79,7 +79,7 @@ static uint64_t mfmsr(uint64_t reg) static uint64_t mtmsr(uint64_t reg) { if (reg > 31) - PR_ERROR("Invalid register specified\n"); + PR_ERROR("Invalid register specified for mtmsr\n"); return MTMSR_OPCODE | (reg << 21); }