From patchwork Tue Sep 12 14:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833084 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=4rxDZJUm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGm4FCSz1ygM for ; Wed, 13 Sep 2023 00:46:08 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xipbjc+gViB1Cs6oCyVWLo13TCWmwxTFelW/golvzmU=; b=4rxDZJUmmHiHrlDuTqtnriT8iJ BxBNGft41sQ2+m8/GbROKbNhhjGwK7GJ3BqDR/ZE+UgGExy/3b9L1ySCowz35TXsE+++cAajx0zMe Ec2x/4qa2Z2qsucRRJpMBdTbQw5/EiJU6dNujiOQAGMdFirAxANGlwuiUWHfP0Bjiliet5FO5bsX1 gJBrXVk61bRuBQ8RuL6GHcf/K/PCG6Toa6xWsDEzarjPAz64GcLgb9PAP2cAr0KXQ93uFDsg5XeoI 7xasoIgy0G8r0oyZBvlGbEXvKidtzv2JjNCNjCvbyVLSljOTv8tFHNu1FkASxqjDIW39sLKd5nDMA x+fZs8lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4cE-003cMP-0G; Tue, 12 Sep 2023 14:43:46 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 11/12] uboot-rockchip: add NanoPi R5C support Date: Tue, 12 Sep 2023 22:42:39 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Add support for the FriendlyARM NanoPi R5C. Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 8 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 269 ++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 5e55077484..1dad3c1e1c 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -127,6 +127,13 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.18.bin endef +define U-Boot/nanopi-r5c-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5c +endef + define U-Boot/nanopi-r5s-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5S @@ -146,6 +153,7 @@ UBOOT_TARGETS := \ roc-cc-rk3328 \ rock64-rk3328 \ rock-pi-e-rk3328 \ + nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..d1a5197e7d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,269 @@ +From 41538742491c46100f570680c02fbdd0d2b6b880 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue, 30 May 2023 15:00:33 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C + +FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. + +Specification: +- Rockchip RK3568 +- 1/4GB LPDDR4X RAM +- 8/32GB eMMC +- SD card slot +- M.2 Connector +- 2x USB 3.0 Port +- 2x 2500 Base-T (PCIe, r8125) +- HDMI 2.0 +- MIPI DSI/CSI +- USB Type C 5V + +The device tree is taken from kernel v6.4-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 + + arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++ + board/rockchip/evb_rk3568/MAINTAINERS | 7 ++ + configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++ + 5 files changed, 208 insertions(+) + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts + create mode 100644 configs/nanopi-r5c-rk3568_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ ++ rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +@@ -0,0 +1,3 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++#include "rk3568-nanopi-r5s-u-boot.dtsi" +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c.dts +@@ -0,0 +1,112 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5C"; ++ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; ++ ++ led-lan { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_reset_pin>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_led_pin: wlan-led-pin { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_reset_pin: pcie20-reset-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig + F: arch/arm/dts/rk3568-evb-boot.dtsi + F: arch/arm/dts/rk3568-evb.dts + ++NANOPI-R5C ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r5c-rk3568_defconfig ++F: arch/arm/dts/rk3568-nanopi-r5c.dts ++F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi ++ + NANOPI-R5S + M: Tianling Shen + S: Maintained +--- /dev/null ++++ b/configs/nanopi-r5c-rk3568_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y