@@ -66,6 +66,15 @@ CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_PROTOCOL=y
@@ -90,7 +99,6 @@ CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
-# CONFIG_BOSCH_BNO055_SERIAL is not set
CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
@@ -113,7 +121,7 @@ CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=5
+CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
@@ -122,6 +130,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
@@ -293,6 +302,7 @@ CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_RK3X=y
CONFIG_IIO=y
+# CONFIG_IIO_SCMI is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INDIRECT_PIO=y
CONFIG_INPUT=y
@@ -301,7 +311,7 @@ CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_MATRIXKMAP=y
-# CONFIG_INPUT_RK805_PWRKEY is not set
+CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
@@ -334,7 +344,6 @@ CONFIG_KSM=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
-# CONFIG_LEDS_PWM_MULTICOLOR is not set
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_PANIC=y
@@ -459,9 +468,9 @@ CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_PCIE=y
-# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PINCTRL=y
@@ -495,10 +504,8 @@ CONFIG_PROC_VMCORE=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
-# CONFIG_PWM_CLK is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_XILINX is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
@@ -518,6 +525,7 @@ CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
@@ -525,6 +533,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
CONFIG_RFS_ACCEL=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
@@ -553,6 +562,7 @@ CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SAS_LIBSAS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_DW=y
@@ -589,7 +599,7 @@ CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_ROCKCHIP=y
-# CONFIG_SPI_ROCKCHIP_SFC is not set
+CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_SPIDEV=y
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
new file mode 100644
@@ -0,0 +1,60 @@
+From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Thu, 2 Feb 2023 08:35:16 +0800
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
+ rockchip platform
+
+For Rockchip platform, DLL bypass bit and start bit need to be set if
+DLL is not locked. And adjust pre-change delay to 0x3 for better signal
+test result.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -48,6 +48,7 @@
+ #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
+ #define DWCMSHC_EMMC_DLL_START_POINT 16
+ #define DWCMSHC_EMMC_DLL_INC 8
++#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
+ #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
+ #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
+ #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
+@@ -60,6 +61,7 @@
+ #define DLL_RXCLK_NO_INVERTER 1
+ #define DLL_RXCLK_INVERTER 0
+ #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
++#define DLL_RXCLK_ORI_GATE BIT(31)
+ #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
+ #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
+ #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
+@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
+ sdhci_writel(host, extra, reg);
+
+ if (clock <= 52000000) {
+- /* Disable DLL and reset both of sample and drive clock */
+- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
++ /*
++ * Disable DLL and reset both of sample and drive clock.
++ * The bypass bit and start bit need to be set if DLL is not locked.
++ */
++ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
++ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
+ sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
+ /*
+@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
+ }
+
+ extra = 0x1 << 16 | /* tune clock stop en */
+- 0x2 << 17 | /* pre-change delay */
++ 0x3 << 17 | /* pre-change delay */
+ 0x3 << 19; /* post-change delay */
+ sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
+
new file mode 100644
@@ -0,0 +1,52 @@
+From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Thu, 9 Mar 2023 17:03:49 -0800
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
+ Rockchip
+
+Currently .get_max_clock returns the current clock rate for cclk_emmc
+on rk35xx, thus max clock gets set to whatever bootloader set it to.
+
+In case of u-boot, it is intentionally reset to 50 MHz if it boots
+from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
+HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
+clears appropriate caps if host->mmc->f_max is < 52MHz
+
+cclk_emmc is not a fixed clock on rk35xx, so using
+sdhci_pltfm_clk_get_max_clock is not appropriate here.
+
+Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
+ return pltfm_host->clock;
+ }
+
++static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
++{
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++
++ return clk_round_rate(pltfm_host->clk, ULONG_MAX);
++}
++
+ static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
+ struct mmc_request *mrq)
+ {
+@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
+ .set_clock = dwcmshc_rk3568_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
++ .get_max_clock = rk35xx_get_max_clock,
+ .reset = rk35xx_sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+ };
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Enable all necessary drivers for the rk356x SoCs, including PHY, SCMI, SPI etc. Also backport 2 upstream patches for sdhci fixes. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> --- target/linux/rockchip/armv8/config-6.1 | 28 ++++++--- ...-Update-DLL-and-pre-change-delay-for.patch | 60 +++++++++++++++++++ ...mshc-properly-determine-max-clock-on.patch | 52 ++++++++++++++++ 3 files changed, 131 insertions(+), 9 deletions(-) create mode 100644 target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch create mode 100644 target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch