diff mbox series

realtek: HPE 1920-24G-PoE+ 370W (JG926A) support

Message ID mailman.112953.1726286862.1280.openwrt-devel@lists.openwrt.org
State Superseded, archived
Headers show
Series realtek: HPE 1920-24G-PoE+ 370W (JG926A) support | expand

Commit Message

Evan Jobling Sept. 14, 2024, 4:07 a.m. UTC 
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Hi All.

I am attempting to send through two patches for adding
support for the JG926A.

The JG925A  (180W model) should be very similar but I don't have
a device to test. I can get the H3C device ID and add it to
the patch set but it would be untested on physical hardware.

I understand there's also work going on for getting the target
onto linux kernel 6.6?

I have two patches prepared  with git format-patch attached.
 I can also email through as separate emails if required?

Your feedback would be appreciated.

Cheers,
Evan.

Comments

Felix Baumann Sept. 14, 2024, 7:26 a.m. UTC | #1 
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Am 14. September 2024 06:07:27 MESZ schrieb Evan Jobling via openwrt-devel <openwrt-devel@lists.openwrt.org>:
>The sender domain has a DMARC Reject/Quarantine policy which disallows
>sending mailing list messages using the original "From" header.
>
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Hi,

just a heads up in-case you missed the mail:
The Realtek target needs help. It needs to be upgraded to Kernel 6.6 like all the other targets.
Else there is a chance it will be dropped so OpenWrt Release 24 can proceed to be branched and later released. The Realtek could still be reintroduced later on, if people owning the device can help put in the work or help with testing.

<https://lists.openwrt.org/pipermail/openwrt-devel/2024-August/043087.html>

If you have further questions feel free to ask via mail or on Github
<https://github.com/openwrt/openwrt/pull/16052> 

Regards
Felix Baumann
Bjørn Mork Sept. 14, 2024, 10:46 a.m. UTC | #2 
The sender domain has a DMARC Reject/Quarantine policy which disallows
sending mailing list messages using the original "From" header.

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Felix Baumann via openwrt-devel <openwrt-devel@lists.openwrt.org>
writes:

> The Realtek target needs help. It needs to be upgraded to Kernel 6.6
> like all the other targets.  Else there is a chance it will be dropped
> so OpenWrt Release 24 can proceed to be branched and later
> released. The Realtek could still be reintroduced later on, if people
> owning the device can help put in the work or help with testing.

Things are not looking that bad any longer, IMHO.  There's a 6.6 PR
ready(?) for merging: https://github.com/openwrt/openwrt/pull/16204

AFACS, the latest revision addresses all comments so far.  Better test
coverage on different hardware and actual use cases would probably be
good though.

So please, everybody: Go test that code now!

That's the best help you currenly can give the target. Remember to
enable v6.6 by setting CONFIG_TESTING_KERNEL=y in .config.  It's so easy
to forget.  Done that several times myself...


Bjørn
diff mbox series

Patch

From d7b3c1209a2db143e6f4ece32d82e5d80af64d0e Mon Sep 17 00:00:00 2001
From: Evan Jobling <evan.jobling@mslsc.com.au>
Date: Sat, 14 Sep 2024 02:31:09 +0000
Subject: [PATCH 1/2] realtek: rtl838x: refactor hpe_1920-24g dts

The HPE JG924A, JG925A and JG926A share the same base.
Prepare base device for adding the PoE enabled switch support.

Signed-off-by: Evan Jobling <evan.jobling@mslsc.com.au>
---
 .../realtek/dts-5.15/rtl8382_hpe_1920-24g.dts | 62 +----------------
 .../dts-5.15/rtl8382_hpe_1920-24g.dtsi        | 68 +++++++++++++++++++
 2 files changed, 69 insertions(+), 61 deletions(-)
 create mode 100644 target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dtsi

diff --git a/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dts b/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dts
index 61781c708e..cc92b144b5 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dts
@@ -1,68 +1,8 @@ 
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "rtl8382_hpe_1920.dtsi"
+#include "rtl8382_hpe_1920-24g.dtsi"
 
 / {
 	compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
 	model = "HPE 1920-24G (JG924A)";
 };
-
-&mdio {
-	EXTERNAL_PHY(0)
-	EXTERNAL_PHY(1)
-	EXTERNAL_PHY(2)
-	EXTERNAL_PHY(3)
-	EXTERNAL_PHY(4)
-	EXTERNAL_PHY(5)
-	EXTERNAL_PHY(6)
-	EXTERNAL_PHY(7)
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(0, 1, qsgmii)
-		SWITCH_PORT(1, 2, qsgmii)
-		SWITCH_PORT(2, 3, qsgmii)
-		SWITCH_PORT(3, 4, qsgmii)
-		SWITCH_PORT(4, 5, qsgmii)
-		SWITCH_PORT(5, 6, qsgmii)
-		SWITCH_PORT(6, 7, qsgmii)
-		SWITCH_PORT(7, 8, qsgmii)
-
-		SWITCH_PORT(8, 9, internal)
-		SWITCH_PORT(9, 10, internal)
-		SWITCH_PORT(10, 11, internal)
-		SWITCH_PORT(11, 12, internal)
-		SWITCH_PORT(12, 13, internal)
-		SWITCH_PORT(13, 14, internal)
-		SWITCH_PORT(14, 15, internal)
-		SWITCH_PORT(15, 16, internal)
-
-		SWITCH_PORT(16, 17, qsgmii)
-		SWITCH_PORT(17, 18, qsgmii)
-		SWITCH_PORT(18, 19, qsgmii)
-		SWITCH_PORT(19, 20, qsgmii)
-		SWITCH_PORT(20, 21, qsgmii)
-		SWITCH_PORT(21, 22, qsgmii)
-		SWITCH_PORT(22, 23, qsgmii)
-		SWITCH_PORT(23, 24, qsgmii)
-
-		SWITCH_PORT(24, 25, qsgmii)
-		SWITCH_PORT(25, 26, qsgmii)
-		SWITCH_PORT(26, 27, qsgmii)
-		SWITCH_PORT(27, 28, qsgmii)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dtsi b/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dtsi
new file mode 100644
index 0000000000..61781c708e
--- /dev/null
+++ b/target/linux/realtek/dts-5.15/rtl8382_hpe_1920-24g.dtsi
@@ -0,0 +1,68 @@ 
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_hpe_1920.dtsi"
+
+/ {
+	compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
+	model = "HPE 1920-24G (JG924A)";
+};
+
+&mdio {
+	EXTERNAL_PHY(0)
+	EXTERNAL_PHY(1)
+	EXTERNAL_PHY(2)
+	EXTERNAL_PHY(3)
+	EXTERNAL_PHY(4)
+	EXTERNAL_PHY(5)
+	EXTERNAL_PHY(6)
+	EXTERNAL_PHY(7)
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		SWITCH_PORT(0, 1, qsgmii)
+		SWITCH_PORT(1, 2, qsgmii)
+		SWITCH_PORT(2, 3, qsgmii)
+		SWITCH_PORT(3, 4, qsgmii)
+		SWITCH_PORT(4, 5, qsgmii)
+		SWITCH_PORT(5, 6, qsgmii)
+		SWITCH_PORT(6, 7, qsgmii)
+		SWITCH_PORT(7, 8, qsgmii)
+
+		SWITCH_PORT(8, 9, internal)
+		SWITCH_PORT(9, 10, internal)
+		SWITCH_PORT(10, 11, internal)
+		SWITCH_PORT(11, 12, internal)
+		SWITCH_PORT(12, 13, internal)
+		SWITCH_PORT(13, 14, internal)
+		SWITCH_PORT(14, 15, internal)
+		SWITCH_PORT(15, 16, internal)
+
+		SWITCH_PORT(16, 17, qsgmii)
+		SWITCH_PORT(17, 18, qsgmii)
+		SWITCH_PORT(18, 19, qsgmii)
+		SWITCH_PORT(19, 20, qsgmii)
+		SWITCH_PORT(20, 21, qsgmii)
+		SWITCH_PORT(21, 22, qsgmii)
+		SWITCH_PORT(22, 23, qsgmii)
+		SWITCH_PORT(23, 24, qsgmii)
+
+		SWITCH_PORT(24, 25, qsgmii)
+		SWITCH_PORT(25, 26, qsgmii)
+		SWITCH_PORT(26, 27, qsgmii)
+		SWITCH_PORT(27, 28, qsgmii)
+
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
-- 
2.39.2