@@ -387,6 +387,15 @@ static void ar934x_set_speed_ge0(int speed)
#define QCA955X_GMAC_REG_SGMII_RESET_TX_CLK_N BIT(1)
#define QCA955X_GMAC_REG_SGMII_RESET_RX_CLK_N BIT(0)
+#define QCA955X_GE0_BASE 0x19000000
+#define QCA955X_GE0_SIZE 0x2F0
+
+#define QCA955X_GE0_IG_ACL_CSR 0x23C
+#define QCA955X_GE0_IG_ACL_DISABLE BIT(0)
+#define QCA955X_GE0_IG_ACL_MAGIC0 BIT(27)
+#define QCA955X_GE0_IG_ACL_MAGIC1 BIT(29)
+#define QCA955X_GE0_IG_ACL_MAGIC2 BIT(30)
+
static void qca955x_set_speed_xmii(int speed)
{
void __iomem *base;
@@ -396,7 +405,14 @@ static void qca955x_set_speed_xmii(int speed)
__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
iounmap(base);
- // TODO: find out if something like qca955x_reset_xmii(); is needed
+ /* WARNING ugly PoC code ahead */
+ base = ioremap_nocache(QCA955X_GE0_BASE, QCA955X_GE0_SIZE);
+ val = QCA955X_GE0_IG_ACL_DISABLE |
+ QCA955X_GE0_IG_ACL_MAGIC0 |
+ QCA955X_GE0_IG_ACL_MAGIC1 |
+ QCA955X_GE0_IG_ACL_MAGIC2;
+ __raw_writel(val, base + QCA955X_GE0_IG_ACL_CSR);
+ iounmap(base);
}
static void qca955x_reset_sgmii(void)