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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Respect the phy-is-integrated property on ethernet-phy nodes. There are RTL8393M switches where the PHYs at address 48 and 49 are provided by an external RTL8214FC. Hardcoding them to use the internal SerDes makes it impossible to use the ports connected to such [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org Respect the phy-is-integrated property on ethernet-phy nodes. There are RTL8393M switches where the PHYs at address 48 and 49 are provided by an external RTL8214FC. Hardcoding them to use the internal SerDes makes it impossible to use the ports connected to such an external PHY. Respect the phy-is-integrated property on ethernet-phy nodes as a first step to support such ports. The potential impact for this should be limited to RTL8393 based switches, and looking at the commit messages and device tree files of the supported switches based on this SoC, the SFP and/or combo ports are either not working (D-Link DGS-1210-52, Netgear GS750E, TP-Link SG2452P/T1600G-52PS), use PHYs at a different address (Panasonic SwitchM48EG PN28480K), or already have the phy-is-integrated property set on the PHYs at address 48 and 49. Signed-off-by: Stijn Tintel Acked-by: Daniel Golle --- .../realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 54e592aeaa..71e7937336 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -1658,7 +1658,7 @@ static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in int err; struct rtl838x_eth_priv *priv = bus->priv; - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) + if (priv->phy_is_internal[mii_id]) return rtl839x_read_sds_phy(mii_id, regnum); if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { @@ -1797,7 +1797,7 @@ static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, struct rtl838x_eth_priv *priv = bus->priv; int err; - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) + if (priv->phy_is_internal[mii_id]) return rtl839x_write_sds_phy(mii_id, regnum, value); if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {