diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network
index 45d7cbc75a4a..864328d6bcf1 100644
--- a/target/linux/ixp4xx/base-files/etc/board.d/02_network
+++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network
@@ -11,6 +11,11 @@ gateworks,gw2358)
 linksys,nslu2)
 	ucidef_set_interface_lan "eth0" "dhcp"
 	;;
+usr,usr8200)
+	# LAN ports connected to eth1 thru the MV88E6060 DSA switch
+	ucidef_set_interface "eth" device "eth1" protocol "none"
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth0"
+	;;
 *)
 	ucidef_set_interface_lan "eth0" "dhcp"
 	;;
diff --git a/target/linux/ixp4xx/config-6.1 b/target/linux/ixp4xx/config-6.1
index 3b47385d6b8d..4c4aa11969ea 100644
--- a/target/linux/ixp4xx/config-6.1
+++ b/target/linux/ixp4xx/config-6.1
@@ -1,4 +1,5 @@
 CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMD_PHY=y
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_IXP4XX=y
diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile
index 0bcabe2db143..c6d4817c966f 100644
--- a/target/linux/ixp4xx/image/Makefile
+++ b/target/linux/ixp4xx/image/Makefile
@@ -74,4 +74,17 @@ define Device/linksys_nslu2
 endef
 TARGET_DEVICES += linksys_nslu2
 
+define Device/usrobotics_usr8200
+	DEVICE_VENDOR := USRobotics
+	DEVICE_MODEL := USR8200
+	# USB2 is compiled in and needs no package
+	DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-r7301 kmod-firewire kmod-firewire-ohci
+	DEVICE_DTS := intel-ixp42x-usrobotics-usr8200
+	KERNEL := kernel-bin | append-dtb
+	IMAGES := kernel.bin rootfs.bin
+	IMAGE/kernel.bin := append-kernel
+	IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k
+endef
+TARGET_DEVICES += usrobotics_usr8200
+
 $(eval $(call BuildImage))
diff --git a/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch b/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
new file mode 100644
index 000000000000..38adecd64fff
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
@@ -0,0 +1,93 @@
+From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 21 Sep 2023 00:12:42 +0200
+Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
+
+This makes it possible to provide basic clock output on pins
+14 and 15. The clocks are typically used by random electronics,
+not modeled in the device tree, so they just need to be provided
+on request.
+
+In order to not disturb old systems that require that the
+hardware defaults are kept in the clock setting bits, we only
+manipulate these if either device tree property is present.
+Once we know a device needs one of the clocks we can set it
+in the device tree.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ixp4xx.c
++++ b/drivers/gpio/gpio-ixp4xx.c
+@@ -38,6 +38,18 @@
+ #define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)
+ #define IXP4XX_GPIO_STYLE_SIZE		3
+ 
++/*
++ * Clock output control register defines.
++ */
++#define IXP4XX_GPCLK_CLK0DC_SHIFT	0
++#define IXP4XX_GPCLK_CLK0TC_SHIFT	4
++#define IXP4XX_GPCLK_CLK0_MASK		GENMASK(7, 0)
++#define IXP4XX_GPCLK_MUX14		BIT(8)
++#define IXP4XX_GPCLK_CLK1DC_SHIFT	16
++#define IXP4XX_GPCLK_CLK1TC_SHIFT	20
++#define IXP4XX_GPCLK_CLK1_MASK		GENMASK(23, 16)
++#define IXP4XX_GPCLK_MUX15		BIT(24)
++
+ /**
+  * struct ixp4xx_gpio - IXP4 GPIO state container
+  * @dev: containing device for this instance
+@@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
+ 	struct ixp4xx_gpio *g;
+ 	struct gpio_irq_chip *girq;
+ 	struct device_node *irq_parent;
++	bool clk_14, clk_15;
++	u32 val;
+ 	int ret;
+ 
+ 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+@@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
+ 	 */
+ 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||
+ 	    of_machine_is_compatible("iom,nas-100d"))
+-		__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
++		val = 0;
++	else
++		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
++
++	/*
++	 * If either clock output is enabled explicitly in the device tree
++	 * we take full control of the clock by masking off all bits for
++	 * the clock control and selectively enabling them. Otherwise
++	 * we leave the hardware default settings.
++	 *
++	 * Enable clock outputs with default timings of requested clock.
++	 * If you need control over TC and DC, add these to the device
++	 * tree bindings and use them here.
++	 */
++	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
++	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
++	if (clk_14 || clk_15) {
++		val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
++		val &= ~IXP4XX_GPCLK_CLK0_MASK;
++		val &= ~IXP4XX_GPCLK_CLK1_MASK;
++		if (clk_14) {
++			val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
++			val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
++			val |= IXP4XX_GPCLK_MUX14;
++		}
++
++		if (clk_15) {
++			val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
++			val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
++			val |= IXP4XX_GPCLK_MUX15;
++		}
++	}
++
++	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);
+ 
+ 	/*
+ 	 * This is a very special big-endian ARM issue: when the IXP4xx is
diff --git a/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch b/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
new file mode 100644
index 000000000000..0ae80d170e49
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
@@ -0,0 +1,260 @@
+From 02693ffdb93bffcbe772bd91a399dabd123b8c19 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Tue, 19 Sep 2023 16:02:15 +0200
+Subject: [PATCH 4/4] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
+
+This is a USRobotics NAS/Firewall/router that has been supported
+by OpenWrt in the past. It had dedicated users so let's get it
+properly supported.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/Makefile                    |   3 +-
+ .../dts/intel-ixp42x-usrobotics-usr8200.dts   | 229 ++++++++++++++++++
+ 2 files changed, 231 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ 	intel-ixp43x-gateworks-gw2358.dtb \
+ 	intel-ixp42x-netgear-wg302v1.dtb \
+ 	intel-ixp42x-arcom-vulcan.dtb \
+-	intel-ixp42x-gateway-7001.dtb
++	intel-ixp42x-gateway-7001.dtb \
++	intel-ixp42x-usrobotics-usr8200.dtb
+ dtb-$(CONFIG_ARCH_KEYSTONE) += \
+ 	keystone-k2hk-evm.dtb \
+ 	keystone-k2l-evm.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for the USRobotics USR8200 firewall
++ * VPN and NAS. Based on know-how from Peter Denison.
++ *
++ * This machine is based on IXP422, the USR internal codename
++ * is "Jeeves".
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "USRobotics USR8200";
++	compatible = "usr,usr8200", "intel,ixp42x";
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	memory@0 {
++		device_type = "memory";
++		reg = <0x00000000 0x4000000>;
++	};
++
++	chosen {
++		bootargs = "console=ttyS0,115200n8";
++		stdout-path = "uart1:115200n8";
++	};
++
++	aliases {
++		/* These are switched around */
++		serial0 = &uart1;
++		serial1 = &uart0;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		ieee1394_led: led-1394 {
++			label = "usr8200:green:1394";
++			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		usb1_led: led-usb1 {
++			label = "usr8200:green:usb1";
++			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		usb2_led: led-usb2 {
++			label = "usr8200:green:usb2";
++			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		wireless_led: led-wireless {
++			/*
++			 * This LED is mounted inside the case but cannot be
++			 * seen from the outside: probably USR planned at one
++			 * point for the device to have a wireless card, then
++			 * changed their mind and didn't mount it, leaving the
++			 * LED in place.
++			 */
++			label = "usr8200:green:wireless";
++			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		pwr_led: led-pwr {
++			label = "usr8200:green:pwr";
++			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	gpio_keys {
++		compatible = "gpio-keys";
++
++		button-reset {
++			wakeup-source;
++			linux,code = <KEY_RESTART>;
++			label = "reset";
++			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	soc {
++		bus@c4000000 {
++			flash@0,0 {
++				compatible = "intel,ixp4xx-flash", "cfi-flash";
++				bank-width = <2>;
++				/* Enable writes on the expansion bus */
++				intel,ixp4xx-eb-write-enable = <1>;
++				/* 16 MB of Flash mapped in at CS0 */
++				reg = <0 0x00000000 0x1000000>;
++
++				partitions {
++					compatible = "redboot-fis";
++					/* Eraseblock at 0x0fe0000 */
++					fis-index-block = <0x7f>;
++				};
++			};
++			rtc@2,0 {
++				/* EPSON RTC7301 DG DIL-capsule */
++				compatible = "epson,rtc7301dg";
++				/*
++				 * These timing settings were found in the boardfile patch:
++				 * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
++				 *                  IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
++				 */
++				intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
++				intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
++				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
++				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
++				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
++				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
++				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
++				intel,ixp4xx-eb-mux-address-and-data = <0>;
++				intel,ixp4xx-eb-ahb-split-transfers = <0>;
++				intel,ixp4xx-eb-write-enable = <1>;
++				intel,ixp4xx-eb-byte-access = <1>;
++				/* 512 bytes at CS2 */
++				reg = <2 0x00000000 0x0000200>;
++				reg-io-width = <1>;
++				native-endian;
++				/* FIXME: try to check if there is an IRQ for the RTC? */
++			};
++		};
++
++		pci@c0000000 {
++			status = "okay";
++
++			/*
++			 * Taken from USR8200 boardfile from OpenWrt
++			 *
++			 * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
++			 * We assume the same IRQ for all pins on the remaining slots, that
++			 * is what the boardfile was doing.
++			 */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0xf800 0 0 7>;
++			interrupt-map =
++			/* IDSEL 14 used for "Wireless" in the board file */
++			<0x7000 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
++			/* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
++			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
++			/* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
++			<0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
++			<0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
++			<0x8000 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
++		};
++
++		gpio@c8004000 {
++			/* Enable clock out on GPIO 15 */
++			intel,ixp4xx-gpio15-clkout;
++		};
++
++		/* EthB WAN */
++		ethernet@c8009000 {
++			status = "okay";
++			queue-rx = <&qmgr 3>;
++			queue-txready = <&qmgr 20>;
++			phy-mode = "rgmii";
++			phy-handle = <&phy9>;
++
++			mdio {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				phy9: ethernet-phy@9 {
++					reg = <9>;
++				};
++
++				/* The switch uses MDIO addresses 16 thru 31 */
++				switch@16 {
++					compatible = "marvell,mv88e6060";
++					reg = <16>;
++
++					ports {
++						#address-cells = <1>;
++						#size-cells = <0>;
++
++						port@0 {
++							reg = <0>;
++							label = "lan1";
++						};
++
++						port@1 {
++							reg = <1>;
++							label = "lan2";
++						};
++
++						port@2 {
++							reg = <2>;
++							label = "lan3";
++						};
++
++						port@3 {
++							reg = <3>;
++							label = "lan4";
++						};
++
++						port@5 {
++							/* Port 5 is the CPU port according to the MV88E6060 datasheet */
++							reg = <5>;
++							phy-mode = "rgmii-id";
++							ethernet = <&ethc>;
++							label = "cpu";
++							fixed-link {
++								speed = <100>;
++								full-duplex;
++							};
++						};
++					};
++				};
++			};
++		};
++
++		/* EthC LAN connected to the Marvell DSA Switch */
++		ethc: ethernet@c800a000 {
++			status = "okay";
++			queue-rx = <&qmgr 4>;
++			queue-txready = <&qmgr 21>;
++			phy-mode = "rgmii";
++			fixed-link {
++				speed = <100>;
++				full-duplex;
++			};
++		};
++	};
++};
diff --git a/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch b/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch
new file mode 100644
index 000000000000..4abc6cdbe4e0
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch
@@ -0,0 +1,132 @@
+From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 23 Sep 2023 20:38:22 +0200
+Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
+
+As we don't specify the MTU in the driver, the framework
+will fall back to 1500 bytes and this doesn't work very
+well when we try to attach a DSA switch:
+
+  eth1: mtu greater than device maximum
+  ixp4xx_eth c800a000.ethernet eth1: error -22 setting
+  MTU to 1504 to include DSA overhead
+
+After locating an out-of-tree patch in OpenWrt I found
+suitable code to set the MTU on the interface and ported
+it and updated it. Now the MTU gets set properly.
+
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
+ 1 file changed, 64 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+@@ -24,6 +24,7 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/dmapool.h>
+ #include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/net_tstamp.h>
+@@ -63,7 +64,15 @@
+ 
+ #define POOL_ALLOC_SIZE		(sizeof(struct desc) * (RX_DESCS + TX_DESCS))
+ #define REGS_SIZE		0x1000
+-#define MAX_MRU			1536 /* 0x600 */
++
++/* MRU is said to be 14320 in a code dump, the SW manual says that
++ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
++ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
++ *
++ * FIXME: we have chosen the safe default (14320) but if you can test
++ * jumboframes, experiment with 16320 and see what happens!
++ */
++#define MAX_MRU			(14320 - VLAN_ETH_HLEN)
+ #define RX_BUFF_SIZE		ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
+ 
+ #define NAPI_WEIGHT		16
+@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
+ 	}
+ }
+ 
++static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
++{
++	struct port *port = netdev_priv(dev);
++	struct npe *npe = port->npe;
++	int framesize, chunks;
++	struct msg msg = {};
++
++	/* adjust for ethernet headers */
++	framesize = new_mtu + VLAN_ETH_HLEN;
++	/* max rx/tx 64 byte chunks */
++	chunks = DIV_ROUND_UP(framesize, 64);
++
++	msg.cmd = NPE_SETMAXFRAMELENGTHS;
++	msg.eth_id = port->id;
++
++	/* Firmware wants to know buffer size in 64 byte chunks */
++	msg.byte2 = chunks << 8;
++	msg.byte3 = chunks << 8;
++
++	msg.byte4 = msg.byte6 = framesize >> 8;
++	msg.byte5 = msg.byte7 = framesize & 0xff;
++
++	if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
++		return -EIO;
++	netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
++		   npe_name(npe), new_mtu);
++
++	return 0;
++}
++
++static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
++{
++	int ret;
++
++	/* MTU can only be changed when the interface is up. We also
++	 * set the MTU from dev->mtu when opening the device.
++	 */
++	if (dev->flags & IFF_UP) {
++		ret = ixp4xx_do_change_mtu(dev, new_mtu);
++		if (ret < 0)
++			return ret;
++	}
++
++	dev->mtu = new_mtu;
++
++	return 0;
++}
++
+ static int eth_open(struct net_device *dev)
+ {
+ 	struct port *port = netdev_priv(dev);
+@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
+ 	if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
+ 		return -EIO;
+ 
++	ixp4xx_do_change_mtu(dev, dev->mtu);
++
+ 	if ((err = request_queues(port)) != 0)
+ 		return err;
+ 
+@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
+ static const struct net_device_ops ixp4xx_netdev_ops = {
+ 	.ndo_open = eth_open,
+ 	.ndo_stop = eth_close,
++	.ndo_change_mtu = ixp4xx_eth_change_mtu,
+ 	.ndo_start_xmit = eth_xmit,
+ 	.ndo_set_rx_mode = eth_set_mcast_list,
+ 	.ndo_eth_ioctl = eth_ioctl,
+@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
+ 	ndev->dev.dma_mask = dev->dma_mask;
+ 	ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
+ 
++	ndev->min_mtu = ETH_MIN_MTU;
++	ndev->max_mtu = MAX_MRU;
++
+ 	netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
+ 
+ 	if (!(port->npe = npe_request(NPE_ID(port->id))))
diff --git a/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch b/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch
new file mode 100644
index 000000000000..8eae06deb616
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch
@@ -0,0 +1,79 @@
+From b09e5ea32e099821b1cddc1e26e625ad994ba11e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 24 Sep 2023 21:20:24 +0200
+Subject: [PATCH] watchdog: ixp4xx: Make sure restart always works
+
+The IXP4xx watchdog in early "A0" silicon is unreliable and
+cannot be registered, however for some systems such as the
+USRobotics USR8200 the watchdog is the only restart option,
+so implement a "dummy" watchdog that can only support restart
+in this case.
+
+Fixes: 1aea522809e6 ("watchdog: ixp4xx: Implement restart")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+Other solutions like implementing a pure restart notifier
+callback catch in the driver is possible, but this method
+will minimize the amount of code and reuse infrastructure
+in the core.
+---
+ drivers/watchdog/ixp4xx_wdt.c | 28 +++++++++++++++++++++++++---
+ 1 file changed, 25 insertions(+), 3 deletions(-)
+
+--- a/drivers/watchdog/ixp4xx_wdt.c
++++ b/drivers/watchdog/ixp4xx_wdt.c
+@@ -105,6 +105,25 @@ static const struct watchdog_ops ixp4xx_
+ 	.owner = THIS_MODULE,
+ };
+ 
++/*
++ * The A0 version of the IXP422 had a bug in the watchdog making
++ * is useless, but we still need to use it to restart the system
++ * as it is the only way, so in this special case we register a
++ * "dummy" watchdog that doesn't really work, but will support
++ * the restart operation.
++ */
++static int ixp4xx_wdt_dummy(struct watchdog_device *wdd)
++{
++	return 0;
++}
++
++static const struct watchdog_ops ixp4xx_wdt_restart_only_ops = {
++	.start = ixp4xx_wdt_dummy,
++	.stop = ixp4xx_wdt_dummy,
++	.restart = ixp4xx_wdt_restart,
++	.owner = THIS_MODULE,
++};
++
+ static const struct watchdog_info ixp4xx_wdt_info = {
+ 	.options = WDIOF_KEEPALIVEPING
+ 		| WDIOF_MAGICCLOSE
+@@ -120,14 +139,17 @@ static void ixp4xx_clock_action(void *d)
+ 
+ static int ixp4xx_wdt_probe(struct platform_device *pdev)
+ {
++	static const struct watchdog_ops *iwdt_ops;
+ 	struct device *dev = &pdev->dev;
+ 	struct ixp4xx_wdt *iwdt;
+ 	struct clk *clk;
+ 	int ret;
+ 
+ 	if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
+-		dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n");
+-		return -ENODEV;
++		dev_err(dev, "Rev. A0 IXP42x CPU detected - only restart supported\n");
++		iwdt_ops = &ixp4xx_wdt_restart_only_ops;
++	} else {
++		iwdt_ops = &ixp4xx_wdt_ops;
+ 	}
+ 
+ 	iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
+@@ -153,7 +175,7 @@ static int ixp4xx_wdt_probe(struct platf
+ 		iwdt->rate = IXP4XX_TIMER_FREQ;
+ 
+ 	iwdt->wdd.info = &ixp4xx_wdt_info;
+-	iwdt->wdd.ops = &ixp4xx_wdt_ops;
++	iwdt->wdd.ops = iwdt_ops;
+ 	iwdt->wdd.min_timeout = 1;
+ 	iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
+ 	iwdt->wdd.parent = dev;
diff --git a/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch b/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch
new file mode 100644
index 000000000000..bf056b89a9e5
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch
@@ -0,0 +1,67 @@
+From a1ab45966e5a21841af58742adf27725e523d303 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 14 Oct 2023 19:53:24 +0200
+Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
+
+The MV88E6060 switch has internal PHY registers at MDIO
+addresses 0x00..0x04. Tie each port to the corresponding
+PHY.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../dts/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
+@@ -165,6 +165,24 @@
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 
++				/*
++				 * PHY 0..4 are internal to the MV88E6060 switch but appear
++				 * as independent devices.
++				 */
++				phy0: ethernet-phy@0 {
++					reg = <0>;
++				};
++				phy1: ethernet-phy@1 {
++					reg = <1>;
++				};
++				phy2: ethernet-phy@2 {
++					reg = <2>;
++				};
++				phy3: ethernet-phy@3 {
++					reg = <3>;
++				};
++
++				/* Altima AMI101L used by the WAN port */
+ 				phy9: ethernet-phy@9 {
+ 					reg = <9>;
+ 				};
+@@ -181,21 +199,25 @@
+ 						port@0 {
+ 							reg = <0>;
+ 							label = "lan1";
++							phy-handle = <&phy0>;
+ 						};
+ 
+ 						port@1 {
+ 							reg = <1>;
+ 							label = "lan2";
++							phy-handle = <&phy1>;
+ 						};
+ 
+ 						port@2 {
+ 							reg = <2>;
+ 							label = "lan3";
++							phy-handle = <&phy2>;
+ 						};
+ 
+ 						port@3 {
+ 							reg = <3>;
+ 							label = "lan4";
++							phy-handle = <&phy3>;
+ 						};
+ 
+ 						port@5 {
