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Thu, 28 Sep 2023 06:28:41 -0700 (PDT) From: Linus Walleij Date: Thu, 28 Sep 2023 15:28:32 +0200 Subject: [PATCH v2 9/9] ixp4xx: Add USRobotics USR8200 support MIME-Version: 1.0 Message-Id: <20230928-ixp4xx-v2-9-ce011eef8239@linaro.org> References: <20230928-ixp4xx-v2-0-ce011eef8239@linaro.org> In-Reply-To: <20230928-ixp4xx-v2-0-ce011eef8239@linaro.org> To: Imre Kaloz , Krzysztof Halasa , Howard Harte , openwrt-devel@lists.openwrt.org X-Mailer: b4 0.12.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_062846_413642_91C47B47 X-CRM114-Status: GOOD ( 31.32 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This brings back USRobotics USR8200 support to the IXP4xx target. Signed-off-by: Linus Walleij --- .../linux/ixp4xx/base-files/etc/board.d/02_network | 5 + target/linux/ixp4xx/config-6.1 | 1 + target/linux/ixp4xx/image/Makefile | 14 ++ ... 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Signed-off-by: Linus Walleij --- .../linux/ixp4xx/base-files/etc/board.d/02_network | 5 + target/linux/ixp4xx/config-6.1 | 1 + target/linux/ixp4xx/image/Makefile | 14 ++ ...p4xx-Handle-clock-output-on-pin-14-and-15.patch | 98 ++++++++ ...003-rtc-rtc7301-Support-byte-addressed-IO.patch | 93 +++++++ ...ixp4xx-Add-USRobotics-USR8200-device-tree.patch | 268 +++++++++++++++++++++ ...5-net-ixp4xx_eth-Support-changing-the-MTU.patch | 135 +++++++++++ ...06-net-phy-amd-Support-the-Altima-AMI101L.patch | 89 +++++++ ...dog-ixp4xx-Make-sure-restart-always-works.patch | 84 +++++++ 9 files changed, 787 insertions(+) diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network index 45d7cbc75a4a..864328d6bcf1 100644 --- a/target/linux/ixp4xx/base-files/etc/board.d/02_network +++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network @@ -11,6 +11,11 @@ gateworks,gw2358) linksys,nslu2) ucidef_set_interface_lan "eth0" "dhcp" ;; +usr,usr8200) + # LAN ports connected to eth1 thru the MV88E6060 DSA switch + ucidef_set_interface "eth" device "eth1" protocol "none" + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth0" + ;; *) ucidef_set_interface_lan "eth0" "dhcp" ;; diff --git a/target/linux/ixp4xx/config-6.1 b/target/linux/ixp4xx/config-6.1 index 3b47385d6b8d..4c4aa11969ea 100644 --- a/target/linux/ixp4xx/config-6.1 +++ b/target/linux/ixp4xx/config-6.1 @@ -1,4 +1,5 @@ CONFIG_ALIGNMENT_TRAP=y +CONFIG_AMD_PHY=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_IXP4XX=y diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile index d61189d09b24..4caf20ded88d 100644 --- a/target/linux/ixp4xx/image/Makefile +++ b/target/linux/ixp4xx/image/Makefile @@ -62,6 +62,7 @@ TARGET_DEVICES += cambria define Device/nslu2 DEVICE_VENDOR := Linksys DEVICE_MODEL := NSLU2 + # USB2 is compiled in and needs no package DEVICE_PACKAGES := apex ixp4xx-microcode-ethernet kmod-rtc-x1205 # Only 32 MB of RAM so not building by default DEFAULT := n @@ -73,4 +74,17 @@ define Device/nslu2 endef TARGET_DEVICES += nslu2 +define Device/usr8200 + DEVICE_VENDOR := USRobotics + DEVICE_MODEL := USR8200 + # USB2 is compiled in and needs no package + DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-r7301 kmod-firewire kmod-firewire-ohci + DEVICE_DTS := intel-ixp42x-usrobotics-usr8200 + KERNEL := kernel-bin | append-dtb + IMAGES := kernel.bin rootfs.bin + IMAGE/kernel.bin := append-kernel + IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k +endef +TARGET_DEVICES += usr8200 + $(eval $(call BuildImage)) diff --git a/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch b/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch new file mode 100644 index 000000000000..78a3df0ab1f3 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch @@ -0,0 +1,98 @@ +From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Thu, 21 Sep 2023 00:12:42 +0200 +Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15 + +This makes it possible to provide basic clock output on pins +14 and 15. The clocks are typically used by random electronics, +not modeled in the device tree, so they just need to be provided +on request. + +In order to not disturb old systems that require that the +hardware defaults are kept in the clock setting bits, we only +manipulate these if either device tree property is present. +Once we know a device needs one of the clocks we can set it +in the device tree. + +Signed-off-by: Linus Walleij +--- + drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 48 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c +index dde6cf3a5779..1ca3217d0aab 100644 +--- a/drivers/gpio/gpio-ixp4xx.c ++++ b/drivers/gpio/gpio-ixp4xx.c +@@ -38,6 +38,18 @@ + #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) + #define IXP4XX_GPIO_STYLE_SIZE 3 + ++/* ++ * Clock output control register defines. ++ */ ++#define IXP4XX_GPCLK_CLK0DC_SHIFT 0 ++#define IXP4XX_GPCLK_CLK0TC_SHIFT 4 ++#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0) ++#define IXP4XX_GPCLK_MUX14 BIT(8) ++#define IXP4XX_GPCLK_CLK1DC_SHIFT 16 ++#define IXP4XX_GPCLK_CLK1TC_SHIFT 20 ++#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16) ++#define IXP4XX_GPCLK_MUX15 BIT(24) ++ + /** + * struct ixp4xx_gpio - IXP4 GPIO state container + * @dev: containing device for this instance +@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) + struct ixp4xx_gpio *g; + struct gpio_irq_chip *girq; + struct device_node *irq_parent; ++ bool clk_14, clk_15; ++ u32 val; + int ret; + + g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); +@@ -231,7 +245,40 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) + */ + if (of_machine_is_compatible("dlink,dsm-g600-a") || + of_machine_is_compatible("iom,nas-100d")) +- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); ++ val = 0; ++ else ++ val = __raw_readl(g->base + IXP4XX_REG_GPCLK); ++ ++ /* ++ * If either clock output is enabled explicitly in the device tree ++ * we take full control of the clock by masking off all bits for ++ * the clock control and selectively enabling them. Otherwise ++ * we leave the hardware default settings. ++ * ++ * Enable clock outputs with default timings of requested clock. ++ * If you need control over TC and DC, add these to the device ++ * tree bindings and use them here. ++ */ ++ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout"); ++ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout"); ++ if (clk_14 || clk_15) { ++ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15); ++ val &= ~IXP4XX_GPCLK_CLK0_MASK; ++ val &= ~IXP4XX_GPCLK_CLK1_MASK; ++ if (clk_14) { ++ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT); ++ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT); ++ val |= IXP4XX_GPCLK_MUX14; ++ } ++ ++ if (clk_15) { ++ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT); ++ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT); ++ val |= IXP4XX_GPCLK_MUX15; ++ } ++ } ++ ++ __raw_writel(val, g->base + IXP4XX_REG_GPCLK); + + /* + * This is a very special big-endian ARM issue: when the IXP4xx is +-- +2.41.0 + diff --git a/target/linux/ixp4xx/patches-6.1/0003-rtc-rtc7301-Support-byte-addressed-IO.patch b/target/linux/ixp4xx/patches-6.1/0003-rtc-rtc7301-Support-byte-addressed-IO.patch new file mode 100644 index 000000000000..70c7057b79fa --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0003-rtc-rtc7301-Support-byte-addressed-IO.patch @@ -0,0 +1,93 @@ +From f7415d445b0f012e371bb92d99c24e2728125299 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Thu, 21 Sep 2023 22:18:12 +0200 +Subject: [PATCH 2/3] rtc: rtc7301: Support byte-addressed IO + +The old RTC7301 driver in OpenWrt used byte access, but the +current mainline Linux driver uses 32bit word access. + +Make this configurable using device properties using the +standard property "reg-io-width" in e.g. device tree. + +This is needed for the USRobotics USR8200 which has the +chip connected using byte accesses. + +Signed-off-by: Linus Walleij +--- + drivers/rtc/rtc-r7301.c | 32 ++++++++++++++++++++++++++++++-- + 1 file changed, 30 insertions(+), 2 deletions(-) + +diff --git a/drivers/rtc/rtc-r7301.c b/drivers/rtc/rtc-r7301.c +index 5dbaeb7af648..843e16966b65 100644 +--- a/drivers/rtc/rtc-r7301.c ++++ b/drivers/rtc/rtc-r7301.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -55,12 +56,23 @@ struct rtc7301_priv { + u8 bank; + }; + +-static const struct regmap_config rtc7301_regmap_config = { ++/* ++ * When the device is memory-mapped, some platforms pack the registers into ++ * 32-bit access using the lower 8 bits at each 4-byte stride, while others ++ * expose them as simply consequitive bytes. ++ */ ++static const struct regmap_config rtc7301_regmap_32_config = { + .reg_bits = 32, + .val_bits = 8, + .reg_stride = 4, + }; + ++static const struct regmap_config rtc7301_regmap_8_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .reg_stride = 1, ++}; ++ + static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg) + { + int reg_stride = regmap_get_reg_stride(priv->regmap); +@@ -356,7 +368,9 @@ static int __init rtc7301_rtc_probe(struct platform_device *dev) + void __iomem *regs; + struct rtc7301_priv *priv; + struct rtc_device *rtc; ++ static const struct regmap_config *mapconf; + int ret; ++ u32 val; + + priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) +@@ -366,8 +380,22 @@ static int __init rtc7301_rtc_probe(struct platform_device *dev) + if (IS_ERR(regs)) + return PTR_ERR(regs); + ++ ret = device_property_read_u32(&dev->dev, "reg-io-width", &val); ++ if (!ret) ++ /* Default to 32bit accesses */ ++ val = 4; ++ ++ switch (val) { ++ case 1: ++ mapconf = &rtc7301_regmap_8_config; ++ break; ++ case 4: ++ default: ++ mapconf = &rtc7301_regmap_32_config; ++ } ++ + priv->regmap = devm_regmap_init_mmio(&dev->dev, regs, +- &rtc7301_regmap_config); ++ mapconf); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + +-- +2.41.0 + diff --git a/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch b/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch new file mode 100644 index 000000000000..812186815df4 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch @@ -0,0 +1,268 @@ +From d975123469a640de77cba9b28c527780953052c9 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Tue, 19 Sep 2023 16:02:15 +0200 +Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree + +This is a USRobotics NAS/Firewall/router that has been supported +by OpenWrt in the past. It had dedicated users so let's get it +properly supported. + +Signed-off-by: Linus Walleij +--- + arch/arm/boot/dts/Makefile | 3 +- + .../dts/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++ + 2 files changed, 231 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 6aa7dc4db2fc..2089038b12ef 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp43x-gateworks-gw2358.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ + intel-ixp42x-arcom-vulcan.dtb \ +- intel-ixp42x-gateway-7001.dtb ++ intel-ixp42x-gateway-7001.dtb \ ++ intel-ixp42x-usrobotics-usr8200.dtb + dtb-$(CONFIG_ARCH_KEYSTONE) += \ + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ +diff --git a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts +new file mode 100644 +index 000000000000..b88ac5c20685 +--- /dev/null ++++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts +@@ -0,0 +1,229 @@ ++// SPDX-License-Identifier: ISC ++/* ++ * Device Tree file for the USRobotics USR8200 firewall ++ * VPN and NAS. Based on know-how from Peter Denison. ++ * ++ * This machine is based on IXP422, the USR internal codename ++ * is "Jeeves". ++ */ ++ ++/dts-v1/; ++ ++#include "intel-ixp42x.dtsi" ++#include ++ ++/ { ++ model = "USRobotics USR8200"; ++ compatible = "usr,usr8200", "intel,ixp42x"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x00000000 0x4000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8"; ++ stdout-path = "uart1:115200n8"; ++ }; ++ ++ aliases { ++ /* These are switched around */ ++ serial0 = &uart1; ++ serial1 = &uart0; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ usb1_led: led-usb1 { ++ label = "usr8200:green:usb1"; ++ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ usb2_led: led-usb2 { ++ label = "usr8200:green:usb2"; ++ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ieee1394_led: led-1394 { ++ label = "usr8200:green:1394"; ++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ wireless_led: led-wireless { ++ /* ++ * This LED is mounted inside the case but cannot be ++ * seen from the outside: probably USR planned at one ++ * point for the device to have a wireless card, then ++ * changed their mind and didn't mount it, leaving the ++ * LED in place. ++ */ ++ label = "usr8200:green:wireless"; ++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ pwr_led: led-pwr { ++ label = "usr8200:red:pwr"; ++ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ button-reset { ++ wakeup-source; ++ linux,code = ; ++ label = "reset"; ++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ soc { ++ bus@c4000000 { ++ flash@0,0 { ++ compatible = "intel,ixp4xx-flash", "cfi-flash"; ++ bank-width = <2>; ++ /* Enable writes on the expansion bus */ ++ intel,ixp4xx-eb-write-enable = <1>; ++ /* 16 MB of Flash mapped in at CS0 */ ++ reg = <0 0x00000000 0x1000000>; ++ ++ partitions { ++ compatible = "redboot-fis"; ++ /* Eraseblock at 0x0fe0000 */ ++ fis-index-block = <0x7f>; ++ }; ++ }; ++ rtc@2,0 { ++ /* EPSON RTC7301 DG DIL-capsule */ ++ compatible = "epson,rtc7301dg"; ++ /* ++ * These timing settings were found in the boardfile patch: ++ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN | ++ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; ++ */ ++ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase ++ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase ++ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase ++ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase ++ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase ++ intel,ixp4xx-eb-cycle-type = <3>; // FIXME: Reserved?? Try 0. ++ intel,ixp4xx-eb-byte-access-on-halfword = <0>; ++ intel,ixp4xx-eb-mux-address-and-data = <0>; ++ intel,ixp4xx-eb-ahb-split-transfers = <0>; ++ intel,ixp4xx-eb-write-enable = <1>; ++ intel,ixp4xx-eb-byte-access = <1>; ++ /* 512 bytes at CS2 */ ++ reg = <2 0x00000000 0x0000200>; ++ reg-io-width = <1>; ++ native-endian; ++ /* FIXME: try to check if there is an IRQ for the RTC? */ ++ }; ++ }; ++ ++ pci@c0000000 { ++ status = "okay"; ++ ++ /* ++ * Taken from USR8200 boardfile from OpenWrt ++ * ++ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16. ++ * We assume the same IRQ for all pins on the remaining slots, that ++ * is what the boardfile was doing. ++ */ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ interrupt-map = ++ /* IDSEL 14 used for "Wireless" in the board file */ ++ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ ++ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */ ++ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */ ++ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */ ++ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */ ++ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */ ++ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */ ++ }; ++ ++ gpio@c8004000 { ++ /* Enable clock out on GPIO 15 */ ++ intel,ixp4xx-gpio15-clkout; ++ }; ++ ++ /* EthB WAN */ ++ ethernet@c8009000 { ++ status = "okay"; ++ queue-rx = <&qmgr 3>; ++ queue-txready = <&qmgr 20>; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy9>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy9: ethernet-phy@9 { ++ reg = <9>; ++ }; ++ ++ /* The switch uses MDIO addresses 16 thru 31 */ ++ switch@16 { ++ compatible = "marvell,mv88e6060"; ++ reg = <16>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ /* Port 5 is the CPU port according to the MV88E6060 datasheet */ ++ reg = <5>; ++ phy-mode = "rgmii-id"; ++ ethernet = <ðc>; ++ label = "cpu"; ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ /* EthC LAN connected to the Marvell DSA Switch */ ++ ethc: ethernet@c800a000 { ++ status = "okay"; ++ queue-rx = <&qmgr 4>; ++ queue-txready = <&qmgr 21>; ++ phy-mode = "rgmii"; ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ }; ++}; +-- +2.41.0 + diff --git a/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch b/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch new file mode 100644 index 000000000000..34fb2606cc83 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch @@ -0,0 +1,135 @@ +From dc40504df75ea47803aeb10572fe7b0376b57522 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Fri, 22 Sep 2023 23:18:22 +0200 +Subject: [PATCH] net: ixp4xx_eth: Support changing the MTU + +As we don't specify the MTU in the driver, the framework +will fall back to 1500 bytes and this doesn't work very +well when we try to attach a DSA switch: + + eth1: mtu greater than device maximum + ixp4xx_eth c800a000.ethernet eth1: error -22 setting + MTU to 1504 to include DSA overhead + +After locating an out-of-tree patch in OpenWrt I found +suitable code to set the MTU on the interface and ported +it and updated it. Now the MTU gets set properly. + +Signed-off-by: Linus Walleij +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 64 +++++++++++++++++++++++- + 1 file changed, 63 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 3b0c5f177447..18e52abc005b 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -63,7 +64,15 @@ + + #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) + #define REGS_SIZE 0x1000 +-#define MAX_MRU 1536 /* 0x600 */ ++ ++/* MRU is said to be 14320 in a code dump, the SW manual says that ++ * MRU/MTU is 16320 and includes VLAN and ethernet headers. ++ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161. ++ * ++ * FIXME: we have chosen the safe default (14320) but if you can test ++ * jumboframes, experiment with 16320 and see what happens! ++ */ ++#define MAX_MRU (14320 - VLAN_ETH_HLEN) + #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) + + #define NAPI_WEIGHT 16 +@@ -1182,6 +1191,53 @@ static void destroy_queues(struct port *port) + } + } + ++static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ struct port *port = netdev_priv(dev); ++ struct npe *npe = port->npe; ++ struct msg msg; ++ /* adjust for ethernet headers */ ++ int framesize = new_mtu + VLAN_ETH_HLEN; ++ /* max rx/tx 64 byte chunks */ ++ int chunks = DIV_ROUND_UP(framesize, 64); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_SETMAXFRAMELENGTHS; ++ msg.eth_id = port->id; ++ ++ /* Firmware wants to know buffer size in 64 byte chunks */ ++ msg.byte2 = chunks << 8; ++ msg.byte3 = chunks << 8; ++ ++ msg.byte4 = msg.byte6 = framesize >> 8; ++ msg.byte5 = msg.byte7 = framesize & 0xff; ++ ++ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH")) ++ return -EIO; ++ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n", ++ npe_name(npe), new_mtu); ++ ++ return 0; ++} ++ ++static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ int ret; ++ ++ /* MTU can only be changed when the interface is up. We also ++ * set the MTU from dev->mtu when opening the device. ++ */ ++ if (dev->flags & IFF_UP) { ++ ret = ixp4xx_do_change_mtu(dev, new_mtu); ++ if (ret < 0) ++ return ret; ++ } ++ ++ dev->mtu = new_mtu; ++ ++ return 0; ++} ++ + static int eth_open(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +@@ -1232,6 +1288,8 @@ static int eth_open(struct net_device *dev) + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) + return -EIO; + ++ ixp4xx_do_change_mtu(dev, dev->mtu); ++ + if ((err = request_queues(port)) != 0) + return err; + +@@ -1374,6 +1432,7 @@ static int eth_close(struct net_device *dev) + static const struct net_device_ops ixp4xx_netdev_ops = { + .ndo_open = eth_open, + .ndo_stop = eth_close, ++ .ndo_change_mtu = ixp4xx_eth_change_mtu, + .ndo_start_xmit = eth_xmit, + .ndo_set_rx_mode = eth_set_mcast_list, + .ndo_eth_ioctl = eth_ioctl, +@@ -1488,6 +1547,9 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) + ndev->dev.dma_mask = dev->dma_mask; + ndev->dev.coherent_dma_mask = dev->coherent_dma_mask; + ++ ndev->min_mtu = ETH_MIN_MTU; ++ ndev->max_mtu = MAX_MRU; ++ + netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT); + + if (!(port->npe = npe_request(NPE_ID(port->id)))) +-- +2.41.0 + diff --git a/target/linux/ixp4xx/patches-6.1/0006-net-phy-amd-Support-the-Altima-AMI101L.patch b/target/linux/ixp4xx/patches-6.1/0006-net-phy-amd-Support-the-Altima-AMI101L.patch new file mode 100644 index 000000000000..020bf31d898a --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0006-net-phy-amd-Support-the-Altima-AMI101L.patch @@ -0,0 +1,89 @@ +From 49e5663b505070424e18099841943f34342aa405 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Sun, 24 Sep 2023 01:09:01 +0200 +Subject: [PATCH] net: phy: amd: Support the Altima AMI101L + +The Altima AC101L is obviously compatible with the AMD PHY, +as seen by reading the datasheet. + +Datasheet: https://docs.broadcom.com/doc/AC101L-DS05-405-RDS.pdf + +Signed-off-by: Linus Walleij +--- + drivers/net/phy/Kconfig | 4 ++-- + drivers/net/phy/amd.c | 33 +++++++++++++++++++++++---------- + 2 files changed, 25 insertions(+), 12 deletions(-) + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 107880d13d21..421d2b62918f 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -69,9 +69,9 @@ config SFP + comment "MII PHY device drivers" + + config AMD_PHY +- tristate "AMD PHYs" ++ tristate "AMD and Altima PHYs" + help +- Currently supports the am79c874 ++ Currently supports the AMD am79c874 and Altima AC101L. + + config MESON_GXL_PHY + tristate "Amlogic Meson GXL Internal PHY" +diff --git a/drivers/net/phy/amd.c b/drivers/net/phy/amd.c +index 001bb6d8bfce..930b15fa6ce9 100644 +--- a/drivers/net/phy/amd.c ++++ b/drivers/net/phy/amd.c +@@ -13,6 +13,7 @@ + #include + #include + ++#define PHY_ID_AC101L 0x00225520 + #define PHY_ID_AM79C874 0x0022561b + + #define MII_AM79C_IR 17 /* Interrupt Status/Control Register */ +@@ -87,19 +88,31 @@ static irqreturn_t am79c_handle_interrupt(struct phy_device *phydev) + return IRQ_HANDLED; + } + +-static struct phy_driver am79c_driver[] = { { +- .phy_id = PHY_ID_AM79C874, +- .name = "AM79C874", +- .phy_id_mask = 0xfffffff0, +- /* PHY_BASIC_FEATURES */ +- .config_init = am79c_config_init, +- .config_intr = am79c_config_intr, +- .handle_interrupt = am79c_handle_interrupt, +-} }; ++static struct phy_driver am79c_drivers[] = { ++ { ++ .phy_id = PHY_ID_AM79C874, ++ .name = "AM79C874", ++ .phy_id_mask = 0xfffffff0, ++ /* PHY_BASIC_FEATURES */ ++ .config_init = am79c_config_init, ++ .config_intr = am79c_config_intr, ++ .handle_interrupt = am79c_handle_interrupt, ++ }, ++ { ++ .phy_id = PHY_ID_AC101L, ++ .name = "AC101L", ++ .phy_id_mask = 0xfffffff0, ++ /* PHY_BASIC_FEATURES */ ++ .config_init = am79c_config_init, ++ .config_intr = am79c_config_intr, ++ .handle_interrupt = am79c_handle_interrupt, ++ }, ++}; + +-module_phy_driver(am79c_driver); ++module_phy_driver(am79c_drivers); + + static struct mdio_device_id __maybe_unused amd_tbl[] = { ++ { PHY_ID_AC101L, 0xfffffff0 }, + { PHY_ID_AM79C874, 0xfffffff0 }, + { } + }; +-- +2.41.0 + diff --git a/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch b/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch new file mode 100644 index 000000000000..03c29e63455b --- /dev/null +++ b/target/linux/ixp4xx/patches-6.1/0007-watchdog-ixp4xx-Make-sure-restart-always-works.patch @@ -0,0 +1,84 @@ +From b09e5ea32e099821b1cddc1e26e625ad994ba11e Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Sun, 24 Sep 2023 21:20:24 +0200 +Subject: [PATCH] watchdog: ixp4xx: Make sure restart always works + +The IXP4xx watchdog in early "A0" silicon is unreliable and +cannot be registered, however for some systems such as the +USRobotics USR8200 the watchdog is the only restart option, +so implement a "dummy" watchdog that can only support restart +in this case. + +Fixes: 1aea522809e6 ("watchdog: ixp4xx: Implement restart") +Signed-off-by: Linus Walleij +--- +Other solutions like implementing a pure restart notifier +callback catch in the driver is possible, but this method +will minimize the amount of code and reuse infrastructure +in the core. +--- + drivers/watchdog/ixp4xx_wdt.c | 28 +++++++++++++++++++++++++--- + 1 file changed, 25 insertions(+), 3 deletions(-) + +diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c +index 607ce4b8df57..c0bf03125ec8 100644 +--- a/drivers/watchdog/ixp4xx_wdt.c ++++ b/drivers/watchdog/ixp4xx_wdt.c +@@ -105,6 +105,25 @@ static const struct watchdog_ops ixp4xx_wdt_ops = { + .owner = THIS_MODULE, + }; + ++/* ++ * The A0 version of the IXP422 had a bug in the watchdog making ++ * is useless, but we still need to use it to restart the system ++ * as it is the only way, so in this special case we register a ++ * "dummy" watchdog that doesn't really work, but will support ++ * the restart operation. ++ */ ++static int ixp4xx_wdt_dummy(struct watchdog_device *wdd) ++{ ++ return 0; ++} ++ ++static const struct watchdog_ops ixp4xx_wdt_restart_only_ops = { ++ .start = ixp4xx_wdt_dummy, ++ .stop = ixp4xx_wdt_dummy, ++ .restart = ixp4xx_wdt_restart, ++ .owner = THIS_MODULE, ++}; ++ + static const struct watchdog_info ixp4xx_wdt_info = { + .options = WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE +@@ -114,14 +133,17 @@ static const struct watchdog_info ixp4xx_wdt_info = { + + static int ixp4xx_wdt_probe(struct platform_device *pdev) + { ++ static const struct watchdog_ops *iwdt_ops; + struct device *dev = &pdev->dev; + struct ixp4xx_wdt *iwdt; + struct clk *clk; + int ret; + + if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) { +- dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n"); +- return -ENODEV; ++ dev_err(dev, "Rev. A0 IXP42x CPU detected - only restart supported\n"); ++ iwdt_ops = &ixp4xx_wdt_restart_only_ops; ++ } else { ++ iwdt_ops = &ixp4xx_wdt_ops; + } + + iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL); +@@ -141,7 +163,7 @@ static int ixp4xx_wdt_probe(struct platform_device *pdev) + iwdt->rate = IXP4XX_TIMER_FREQ; + + iwdt->wdd.info = &ixp4xx_wdt_info; +- iwdt->wdd.ops = &ixp4xx_wdt_ops; ++ iwdt->wdd.ops = iwdt_ops; + iwdt->wdd.min_timeout = 1; + iwdt->wdd.max_timeout = U32_MAX / iwdt->rate; + iwdt->wdd.parent = dev; +-- +2.41.0 +