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Fri, 17 Jul 2020 00:23:54 -0700 (PDT) From: Brian Norris To: openwrt-devel@lists.openwrt.org Subject: [PATCH] ipq40xx: add open-drain support to pinctrl-msm Date: Fri, 17 Jul 2020 07:23:48 +0000 Message-Id: <20200717072348.1571186-1-computersforpeace@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_032358_998096_0ABDEEE7 X-CRM114-Status: GOOD ( 15.70 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:641 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [computersforpeace[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Brian Norris Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org Submitted upstream. Shouldn't affect existing devices, but enables new device support. https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/ Currently queued for-next: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=13355ca35cd16f5024655ac06e228b3c199e52a9 Signed-off-by: Brian Norris --- Submitting this separately, partly because the device-support patches are a bit bigger and likely will take a little work. .../090-pinctrl-msm-open-drain.patch | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch diff --git a/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch b/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch new file mode 100644 index 000000000000..9bb05f32844a --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch @@ -0,0 +1,90 @@ +From 5b08c1d567ee8e6af94696b3e549997cbdb2bb80 Mon Sep 17 00:00:00 2001 +From: Jaiganesh Narayanan +Date: Thu, 1 Sep 2016 10:40:38 +0530 +Subject: [PATCH] pinctrl: qcom: ipq4019: add open drain support + +Signed-off-by: Jaiganesh Narayanan +[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based + WiFi APs. ] +Signed-off-by: Brian Norris +--- +https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/ + + drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 + + drivers/pinctrl/qcom/pinctrl-msm.c | 13 +++++++++++++ + drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ + 3 files changed, 16 insertions(+) + +diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c +index 8bdb5bd393d2..63915cb210ff 100644 +--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c ++++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c +@@ -254,6 +254,7 @@ DECLARE_QCA_GPIO_PINS(99); + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ ++ .od_bit = 12, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ +diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c +index 83b7d64bc4c1..dac0404dadf4 100644 +--- a/drivers/pinctrl/qcom/pinctrl-msm.c ++++ b/drivers/pinctrl/qcom/pinctrl-msm.c +@@ -233,6 +233,10 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, + *bit = g->pull_bit; + *mask = 3; + break; ++ case PIN_CONFIG_DRIVE_OPEN_DRAIN: ++ *bit = g->od_bit; ++ *mask = 1; ++ break; + case PIN_CONFIG_DRIVE_STRENGTH: + *bit = g->drv_bit; + *mask = 7; +@@ -310,6 +314,12 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, + if (!arg) + return -EINVAL; + break; ++ case PIN_CONFIG_DRIVE_OPEN_DRAIN: ++ /* Pin is not open-drain */ ++ if (!arg) ++ return -EINVAL; ++ arg = 1; ++ break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = msm_regval_to_drive(arg); + break; +@@ -382,6 +392,9 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, + else + arg = MSM_PULL_UP; + break; ++ case PIN_CONFIG_DRIVE_OPEN_DRAIN: ++ arg = 1; ++ break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* Check for invalid values */ + if (arg > 16 || arg < 2 || (arg % 2) != 0) +diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h +index 9452da18a78b..dc7f8c84744b 100644 +--- a/drivers/pinctrl/qcom/pinctrl-msm.h ++++ b/drivers/pinctrl/qcom/pinctrl-msm.h +@@ -38,6 +38,7 @@ struct msm_function { + * @mux_bit: Offset in @ctl_reg for the pinmux function selection. + * @pull_bit: Offset in @ctl_reg for the bias configuration. + * @drv_bit: Offset in @ctl_reg for the drive strength configuration. ++ * @od_bit: Offset in @ctl_reg for controlling open drain. + * @oe_bit: Offset in @ctl_reg for controlling output enable. + * @in_bit: Offset in @io_reg for the input bit value. + * @out_bit: Offset in @io_reg for the output bit value. +@@ -75,6 +76,7 @@ struct msm_pingroup { + unsigned pull_bit:5; + unsigned drv_bit:5; + ++ unsigned od_bit:5; + unsigned oe_bit:5; + unsigned in_bit:5; + unsigned out_bit:5; +-- +2.17.1 +