From patchwork Wed Jul 8 12:00:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Fertser X-Patchwork-Id: 492878 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BB7F11402B5 for ; Wed, 8 Jul 2015 22:07:23 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=QvuHvY1P; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 1FF8028BDEA; Wed, 8 Jul 2015 14:06:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 1C63B28BDB7 for ; Wed, 8 Jul 2015 14:06:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 CL_IP_EQ_HELO_IP=-2 (check from: .gmail. - helo: .mail-la0-f52.google. - helo-domain: .google.) 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[2001:470:26:54b:250:70ff:fee7:41ec]) by smtp.gmail.com with ESMTPSA id br6sm557899lbb.45.2015.07.08.05.06.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Jul 2015 05:06:58 -0700 (PDT) Received: from home.paul.comp (localhost [127.0.0.1]) by home.paul.comp (8.14.4/8.14.4/Debian-8) with ESMTP id t68C6sVf005400; Wed, 8 Jul 2015 15:06:54 +0300 Received: (from paul@localhost) by home.paul.comp (8.14.4/8.14.4/Submit) id t68C6rUZ005399; Wed, 8 Jul 2015 15:06:53 +0300 Message-Id: <201507081206.t68C6rUZ005399@home.paul.comp> To: ldy647 From: Paul Fertser Gcc: nnfolder+archive:sent.2015-07 Date: Wed, 08 Jul 2015 15:00:19 +0300 Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] Rebooting boards with > 16M SPI flash (was: Re: help) X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Hi, ldy647 writes: > recently, when we install our wireless router, we found when we run > the reboot command, the board couldn't restart. We hope you could lend > us a hand to solve this problem. We'll be quite grateful for what you > do for us. Apparently MT7620 can't handle 4 byte addressing mode of the flash memory on hardware (probably ROM bootloader) level so it needs to be reset somehow prior to resetting the SoC. Some SoCs have a special output from the watchdog to reset all the on-board peripherals, it should be connected to the !RESET pin of the flash as well. And the kernel should then use the watchdog driver to cause a reboot. As a workaround when hardware modification is not possible and the flash IC supports a reset command, you can use a patch like this (in some cases when the kernel is completely stuck it won't help to reboot of course, as the watchdog will fire on hardware level automatically, if configured): diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index b298466..932f307 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,9 @@ /* Used for Spansion flashes only. */ #define OPCODE_BRWR 0x17 /* Bank register write */ +#define OPCODE_RESET_ENABLE 0x66 +#define OPCODE_RESET 0x99 + /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ #define SR_WEL 2 /* Write enable latch */ @@ -907,6 +911,21 @@ static const struct spi_device_id *jedec_probe(struct spi_device *spi) return ERR_PTR(-ENODEV); } +static int m25p80_reboot(struct notifier_block *nb, unsigned long val, + void *v) +{ + struct mtd_info *mtd; + + mtd = container_of(nb, struct mtd_info, reboot_notifier); + struct m25p *flash = mtd_to_m25p(mtd); + + flash->command[0] = OPCODE_RESET_ENABLE; + spi_write(flash->spi, flash->command, 1); + flash->command[0] = OPCODE_RESET; + spi_write(flash->spi, flash->command, 1); + + return NOTIFY_DONE; +} /* * board specific setup should have ensured the SPI clock used here @@ -1010,6 +1029,7 @@ static int m25p_probe(struct spi_device *spi) flash->mtd.size = info->sector_size * info->n_sectors; flash->mtd._erase = m25p80_erase; flash->mtd._read = m25p80_read; + flash->mtd.reboot_notifier.notifier_call = m25p80_reboot; /* flash protection support for STmicro chips */ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { @@ -1085,6 +1105,7 @@ static int m25p_probe(struct spi_device *spi) flash->mtd.eraseregions[i].numblocks); + register_reboot_notifier(&flash->mtd.reboot_notifier); /* partitions should match sector boundaries; and it may be good to * use readonly partitions for writeprotected sectors (BP2..BP0). */ @@ -1099,6 +1120,8 @@ static int m25p_remove(struct spi_device *spi) struct m25p *flash = dev_get_drvdata(&spi->dev); int status; + unregister_reboot_notifier(&flash->mtd.reboot_notifier); + /* Clean up MTD stuff. */ status = mtd_device_unregister(&flash->mtd); if (status == 0) {