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[87.158.109.201]) by smtp.gmail.com with ESMTPSA id cz3sm15686419wjb.14.2016.05.19.11.21.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 May 2016 11:21:58 -0700 (PDT) From: Sven Eckelmann To: openwrt-devel@lists.openwrt.org Date: Thu, 19 May 2016 20:20:59 +0200 Message-Id: <1463682077-19339-16-git-send-email-sven.eckelmann@open-mesh.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com> References: <1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com> Subject: [OpenWrt-Devel] [PATCH CC 16/34] ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR900 X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sven Eckelmann MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" The MR900 must unset some bits in ETH_CFG which were set by u-boot to work correctly under OpenWrt. But the global function ath79_setup_qca955x_eth_cfg will not unset all of them to increase the backward compatiblity with older mach-* files. A private (simplified) version for MR900 can be used instead. Signed-off-by: Sven Eckelmann Backport of r49069 --- .../ar71xx/files/arch/mips/ath79/mach-mr900.c | 24 +++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c index 3634bf0..b439f58 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c @@ -110,6 +110,28 @@ static struct mdio_board_info mr900_mdio0_info[] = { }, }; +static void __init mr900_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, + unsigned int rxdv, + unsigned int txd, + unsigned int txe) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + static void __init mr900_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); @@ -139,7 +161,7 @@ static void __init mr900_setup(void) } pdata->use_eeprom = true; - ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(mr900_mdio0_info,