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[87.158.109.201]) by smtp.gmail.com with ESMTPSA id h4sm15670047wjz.20.2016.05.19.11.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 May 2016 11:21:55 -0700 (PDT) From: Sven Eckelmann To: openwrt-devel@lists.openwrt.org Date: Thu, 19 May 2016 20:20:57 +0200 Message-Id: <1463682077-19339-14-git-send-email-sven.eckelmann@open-mesh.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com> References: <1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com> Subject: [OpenWrt-Devel] [PATCH CC 14/34] ar71xx: Use PHY fixups for Open Mesh MR900 X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sven Eckelmann MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" The delays of PHY/MAC on the MR900 are done by u-boot and OpenWrt in different ways. u-boot only modifies the ETH_CFG of the QCA955x based on the link speed. But OpenWrt can only modify the PHY delays based on the link speed. This can lead to communication problems when u-boot initializes the ETH_CFG for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY delays to an incompatible value. Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and only rely on the AT803x PHY settings. Signed-off-by: Sven Eckelmann Backport of r49030 --- .../ar71xx/files/arch/mips/ath79/mach-mr900.c | 25 +++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c index 9c3164d..3634bf0 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c @@ -23,6 +23,7 @@ #include #include +#include #include "common.h" #include "dev-ap9x-pci.h" @@ -94,15 +95,30 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = { }, }; +static struct at803x_platform_data mr900_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mr900_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 5, + .platform_data = &mr900_at803x_data, + }, +}; + static void __init mr900_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 mac[6], pcie_mac[6]; struct ath9k_platform_data *pdata; - ath79_eth0_pll_data.pll_1000 = 0xbe000101; - ath79_eth0_pll_data.pll_100 = 0x80000101; - ath79_eth0_pll_data.pll_10 = 0x80001313; + ath79_eth0_pll_data.pll_1000 = 0xae000000; + ath79_eth0_pll_data.pll_100 = 0xa0000101; + ath79_eth0_pll_data.pll_10 = 0xa0001313; ath79_register_m25p80(NULL); @@ -126,6 +142,9 @@ static void __init mr900_setup(void) ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(mr900_mdio0_info, + ARRAY_SIZE(mr900_mdio0_info)); + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0); /* GMAC0 is connected to the RMGII interface */