From patchwork Tue Apr 5 13:32:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Eckelmann X-Patchwork-Id: 606468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (caladan.dune.hu [78.24.191.180]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qfVJ55m19z9t3Z for ; Tue, 5 Apr 2016 23:36:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=open-mesh-com.20150623.gappssmtp.com header.i=@open-mesh-com.20150623.gappssmtp.com header.b=Dss9izS9; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 47A9FB91C00; Tue, 5 Apr 2016 15:32:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on arrakis.dune.hu X-Spam-Level: ** X-Spam-Status: No, score=2.4 required=5.0 tests=RDNS_NONE,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.1 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP; Tue, 5 Apr 2016 15:32:56 +0200 (CEST) Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id D54A8B91BFB for ; Tue, 5 Apr 2016 15:32:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 CL_IP_EQ_HELO_IP=-2 (check from: .open-mesh. - helo: .mail-wm0-f52.google. - helo-domain: .google.) FROM/MX_MATCHES_HELO(DOMAIN)=-2; rate: -7 Received: from mail-wm0-f52.google.com (unknown [74.125.82.52]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Tue, 5 Apr 2016 15:32:46 +0200 (CEST) Received: by mail-wm0-f52.google.com with SMTP id l6so23911391wml.1 for ; Tue, 05 Apr 2016 06:32:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=open-mesh-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dhfltPVfWzHjTbEJcMZ+xRRPKBPKDXxTPD96TiPthEs=; b=Dss9izS95z8+2ru6u3pP9MIbofcScaOvpnKwPEj8psVYB7Z2W/3XJR4U4PGvRH12j/ QROQQuadLwvM1+FX5VWzFXvz1QadcXHaG3S2c5EvU026P/IfB0ylhbDdltQ6YNszfB2O 6nu24Z6dTeg3pkhXckFTa3+KAs7bk/QgFXVAzYXHACkqA3sB+9JbCLuW3XuHa9kBXALZ AbT/LFONv3r+k7elTe5hRi6zqToh09q12g/U36U2P6rbmC8SeSNqwR8gR/KFw3+K+vti I3DI6KHGe76mJmNsUbxInGmJ8n8tMw7B+xk32iOB72Rt8bYXpGO9yoOYbDe/soeq+O+D WAxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dhfltPVfWzHjTbEJcMZ+xRRPKBPKDXxTPD96TiPthEs=; b=m/5e4TIpzegr5jFM3+9/7BB0H8zxcg00wIpnhgLyTrmTZFl+uQO9HJRXlg4ftgK3SQ Shkit0Gr7Va65+/MP0wueEmAkL0k3MfWHU+2oCB3Rs94WlAp6eZ+JKbGB4qKQJMHtvhU IcPULasQNcvvqQQYbl5G/7ilne9jgW7b69Ioq5KOex3mVfA+DBX6GdRoV0khy8b4m1zX FzNImI3Dl0BDPnuKuTckMcHgflQgGEN89XXwgHXAnaETYTpf7ROetQQM2/dokcQ8Cyz8 D4K7e9JCWv93Od2eqb9Ck5WC8+IR1Acj/Bjtoo3uVASvjAmr/QfefeUh/2YGukk66i2+ 2dwA== X-Gm-Message-State: AD7BkJLATNPojO5Bmz4QnNpRr86v5rs8XFP8562D173S494rrq1o0sHLrsnnkujJR0tiPgqU X-Received: by 10.194.76.72 with SMTP id i8mr20846410wjw.117.1459863166030; Tue, 05 Apr 2016 06:32:46 -0700 (PDT) Received: from sven-desktop.home.narfation.org (x5d84b455.dyn.telefonica.de. [93.132.180.85]) by smtp.gmail.com with ESMTPSA id g3sm34714412wjw.31.2016.04.05.06.32.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Apr 2016 06:32:45 -0700 (PDT) From: Sven Eckelmann X-Google-Original-From: Sven Eckelmann To: openwrt-devel@lists.openwrt.org Date: Tue, 5 Apr 2016 15:32:13 +0200 Message-Id: <1459863133-26810-6-git-send-email-sven@open-mesh.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1459863133-26810-1-git-send-email-sven@open-mesh.com> References: <1459863133-26810-1-git-send-email-sven@open-mesh.com> Subject: [OpenWrt-Devel] [RFC v2 6/6] ar71xx: Reset QCA955x SGMII link on speed change X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sven Eckelmann , Antonio Quartulli MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" From: Sven Eckelmann The SGMII link of the QCA955x seems to be unstable when the PHY changes the link speed. Reseting the SGMII and the PHY management control seems to resolve this problem. This was observed with an AR8033 and QCA9558 Signed-off-by: Sven Eckelmann --- v2: - Split into multiple patches and adjust slightly to look more like an OpenWrt patch The code of this RFC is not meant to be an actual patch. It should show what the u-boot for QCA955x does and what seemed to work(tm) in my limited tests. It would be interesting to know whether this was also noticed by other people and how they fixed it (when they fixed it). If it is already known than it would maybe good to find a better way to integrate it with ag71xx. Right now it just uses the set_speed callback to start the reset. .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index bfcc82f..f2e88dd 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -383,6 +383,81 @@ static void qca955x_set_speed_xmii(int speed) iounmap(base); } +static void qca955x_reset_sgmii(void) +{ + void __iomem *base; + int count = 0; + u32 status; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = QCA955X_MR_AN_CONTROL_AN_ENABLE | + QCA955X_MR_AN_CONTROL_PHY_RESET; + __raw_writel(t, base + QCA955X_GMAC_REG_MR_AN_CONTROL); + udelay(10); + + t = QCA955X_MR_AN_CONTROL_AN_ENABLE; + __raw_writel(t, base + QCA955X_GMAC_REG_MR_AN_CONTROL); + + t = 0; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = QCA955X_SGMII_RESET_HW_RX_125M; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = QCA955X_SGMII_RESET_HW_RX_125M | + QCA955X_SGMII_RESET_RX_125M; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = QCA955X_SGMII_RESET_HW_RX_125M | + QCA955X_SGMII_RESET_TX_125M | + QCA955X_SGMII_RESET_RX_125M; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = QCA955X_SGMII_RESET_HW_RX_125M | + QCA955X_SGMII_RESET_TX_125M | + QCA955X_SGMII_RESET_RX_125M | + QCA955X_SGMII_RESET_RX_CLK; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = QCA955X_SGMII_RESET_HW_RX_125M | + QCA955X_SGMII_RESET_TX_125M | + QCA955X_SGMII_RESET_RX_125M | + QCA955X_SGMII_RESET_RX_CLK | + QCA955X_SGMII_RESET_TX_CLK; + __raw_writel(t, base + QCA955X_GMAC_REG_SGMII_RESET); + + t = __raw_readl(base + QCA955X_GMAC_REG_MR_AN_CONTROL); + t &= ~QCA955X_MR_AN_CONTROL_PHY_RESET; + __raw_writel(t, base + QCA955X_GMAC_REG_MR_AN_CONTROL); + udelay(100); + + status = __raw_readl(base + QCA955X_GMAC_REG_SGMII_DEBUG); + status &= 0xff; + while (status != 0xf && status != 0x10) { + t = __raw_readl(base + QCA955X_GMAC_REG_MR_AN_CONTROL); + t |= QCA955X_MR_AN_CONTROL_PHY_RESET; + __raw_writel(t, base + QCA955X_GMAC_REG_MR_AN_CONTROL); + + udelay(100); + + t = __raw_readl(base + QCA955X_GMAC_REG_MR_AN_CONTROL); + t &= ~QCA955X_MR_AN_CONTROL_PHY_RESET; + __raw_writel(t, base + QCA955X_GMAC_REG_MR_AN_CONTROL); + + if (count++ >= 20) + break; + + mdelay(10); + + status = __raw_readl(base + QCA955X_GMAC_REG_SGMII_DEBUG); + status &= 0xff; + } + + iounmap(base); +} + static void qca955x_set_speed_sgmii(int speed) { void __iomem *base; @@ -391,6 +466,8 @@ static void qca955x_set_speed_sgmii(int speed) base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); iounmap(base); + + qca955x_reset_sgmii(); } static void qca956x_set_speed_sgmii(int speed)