@@ -259,6 +259,10 @@ ag71xx_ring_size_order(int size)
#define AG71XX_REG_RX_SM 0x01b0
#define AG71XX_REG_TX_SM 0x01b4
+#define QCA955X_REG_IG_ACL 0x23c
+
+#define QCA955X_FRA_DISABLE 0x60000000
+
#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
@@ -376,6 +380,7 @@ static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
case AG71XX_REG_MII_CFG:
+ case QCA955X_REG_IG_ACL:
break;
default:
@@ -474,6 +474,9 @@ static void ag71xx_hw_setup(struct ag71xx *ag)
}
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
+
+ if (pdata->is_qca955x && pdata->gmac_num == 0)
+ ag71xx_sb(ag, QCA955X_REG_IG_ACL, QCA955X_FRA_DISABLE);
}
static void ag71xx_hw_init(struct ag71xx *ag)