From patchwork Sun Oct 11 03:54:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingyu Li X-Patchwork-Id: 528706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D17681402B9 for ; Sun, 11 Oct 2015 14:57:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=NbWcmvQp; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 3F66B28BC2C; Sun, 11 Oct 2015 05:54:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id DC53B283FA7 for ; Sun, 11 Oct 2015 05:53:25 +0200 (CEST) X-policyd-weight: using cached result; rate:hard: -8.5 Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Sun, 11 Oct 2015 05:53:18 +0200 (CEST) Received: by padhy16 with SMTP id hy16so122690616pad.1 for ; Sat, 10 Oct 2015 20:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IkVFsh5vh3jSFjkZ8wLZ2kRN9znfYu2kep8l7knjL5A=; b=NbWcmvQpyAz1JbEWQ9R1lFD3H7PNRPuzq4ArjDa7/rrdYrbD7BZFjEAAUwd0g1c5FO yJMxvhFCa8kpVKmcDPHZicf9k7gGnv8cRwNdkDORyCyFvl+ZLFsoX0ecRdXh09zasn9A K/z9UC8pChJp3TIpQUjetwadmJtr82mUkSq9euAPQsd1miujL4x9piwEI3lZT0PPnSfO MdvAuJ+jBaNWPRRrUBC7UdNuTzZEn1REQjSBbBoR+cDBfC0kUvvmwOh9TAHp0Yht8vtL R0awX2jojpB1Yx3hkoX/zEoKHHPe/X5QdImp8Fr4bz8TEI5IqHpttp9NLhGJN8fCb18s 9rzg== X-Received: by 10.66.240.37 with SMTP id vx5mr25806855pac.76.1444535687399; Sat, 10 Oct 2015 20:54:47 -0700 (PDT) Received: from localhost.localdomain (f45hc114.RAS.nctu.edu.tw. [140.113.45.114]) by smtp.gmail.com with ESMTPSA id ux7sm10833184pac.10.2015.10.10.20.54.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Oct 2015 20:54:46 -0700 (PDT) From: Michael Lee To: blogic@openwrt.org Date: Sun, 11 Oct 2015 11:54:30 +0800 Message-Id: <1444535674-3117-4-git-send-email-igvtee@gmail.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1444535674-3117-1-git-send-email-igvtee@gmail.com> References: <1444535674-3117-1-git-send-email-igvtee@gmail.com> Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 4/8] ramips: improve mt7621 spi setup X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" check word sizes, set spi polarity and enable more buffer mode Signed-off-by: Michael Lee --- ...0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 35 +++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch index 71eba30..0ea0508 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o --- /dev/null +++ b/drivers/spi/spi-mt7621.c -@@ -0,0 +1,532 @@ +@@ -0,0 +1,565 @@ +/* + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver + * @@ -167,6 +167,20 @@ + iowrite32(val, rs->base + reg); +} + ++static inline void mt7621_spi_setbits(struct mt7621_spi *rs, u32 reg, u32 mask) ++{ ++ void __iomem *addr = rs->base + reg; ++ ++ iowrite32((ioread32(addr) | mask), addr); ++} ++ ++static inline void mt7621_spi_clrbits(struct mt7621_spi *rs, u32 reg, u32 mask) ++{ ++ void __iomem *addr = rs->base + reg; ++ ++ iowrite32((ioread32(addr) & ~mask), addr); ++} ++ +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) +{ + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER); @@ -437,6 +451,7 @@ +static int mt7621_spi_setup(struct spi_device *spi) +{ + struct spi_master *master = spi->master; ++ struct mt7621_spi *rs = spi_master_get_devdata(master); + + if ((spi->max_speed_hz > master->max_speed_hz) || + (spi->max_speed_hz < master->min_speed_hz)) { @@ -445,6 +460,24 @@ + return -EINVAL; + } + ++ if (!(master->bits_per_word_mask & ++ BIT(spi->bits_per_word - 1))) { ++ dev_err(&spi->dev, "invalide bits_per_word %d\n", ++ spi->bits_per_word); ++ return -EINVAL; ++ } ++ ++ /* chip polarity */ ++ if (spi->mode & SPI_CS_HIGH) ++ mt7621_spi_setbits(rs, MT7621_SPI_POLAR, ++ (SPIPOL_CSPOL_HIGH << spi->chip_select)); ++ else ++ mt7621_spi_clrbits(rs, MT7621_SPI_POLAR, ++ (SPIPOL_CSPOL_HIGH << spi->chip_select)); ++ ++ /* enable more buffer mode */ ++ mt7621_spi_setbits(rs, MT7621_SPI_MASTER, SPIMASTER_MB_MODE); ++ + return 0; +} +