From patchwork Sun Oct 11 03:54:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingyu Li X-Patchwork-Id: 528705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 040411402B9 for ; Sun, 11 Oct 2015 14:56:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=tuMyf40P; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 0344B287562; Sun, 11 Oct 2015 05:54:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id D207E283FA5 for ; Sun, 11 Oct 2015 05:53:20 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Sun, 11 Oct 2015 05:53:18 +0200 (CEST) Received: by padhy16 with SMTP id hy16so122690415pad.1 for ; Sat, 10 Oct 2015 20:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nktIX0Udjh6RoGcghycl6X77J7slAYkhhyYNA5kE0iM=; b=tuMyf40PS4nZG/FdXUGd6A2aqi74D7jENbHxUNTzr0ZvY5Snj3kc8X1m4YHp28iVo2 J37gZm0BLh2EDk+XjvYzB64GwiBcGQJPGwajDGXn2k3DscqslvkW9pjV5ebRnsBa1WUc ZIgZPcxk/UzK+dTjcyrkvJaZfYYRZt69s8M0yNSQ6xDal045PrGvxGqwcu9WRprOvRD4 xpf3dlQfroWjmkeZ92xHAws9LoaSSEJobehlf1i/rRC0hwJhiz6kBTdsufIxTtcwnLBy Cf4i+8Dn7Aklg6FyP1QM8YlKquUh2YwPZeu0nc1VjJJIeBrdsIvdinPXfAiVk+G+nS9F 8biw== X-Received: by 10.68.137.3 with SMTP id qe3mr26549140pbb.26.1444535686228; Sat, 10 Oct 2015 20:54:46 -0700 (PDT) Received: from localhost.localdomain (f45hc114.RAS.nctu.edu.tw. [140.113.45.114]) by smtp.gmail.com with ESMTPSA id ux7sm10833184pac.10.2015.10.10.20.54.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Oct 2015 20:54:45 -0700 (PDT) From: Michael Lee To: blogic@openwrt.org Date: Sun, 11 Oct 2015 11:54:29 +0800 Message-Id: <1444535674-3117-3-git-send-email-igvtee@gmail.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1444535674-3117-1-git-send-email-igvtee@gmail.com> References: <1444535674-3117-1-git-send-email-igvtee@gmail.com> Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 3/8] ramips: clean up mt7621 spi probe/remove X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" * fill struct according to the member order * add error clean up * set min/max spi speed. so we don't need to check again Signed-off-by: Michael Lee --- ...0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 79 ++++++++++------------ 1 file changed, 37 insertions(+), 42 deletions(-) diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch index 3304ac5..71eba30 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o --- /dev/null +++ b/drivers/spi/spi-mt7621.c -@@ -0,0 +1,537 @@ +@@ -0,0 +1,532 @@ +/* + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver + * @@ -147,13 +147,9 @@ +struct mt7621_spi { + struct spi_master *master; + void __iomem *base; -+ unsigned int sys_freq; + unsigned int speed; + u16 wait_loops; + struct clk *clk; -+ spinlock_t lock; -+ -+ struct mt7621_spi_ops *ops; +}; + +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi) @@ -205,15 +201,9 @@ + + dev_dbg(&spi->dev, "speed:%u\n", speed); + -+ rate = DIV_ROUND_UP(rs->sys_freq, speed); ++ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed); + dev_dbg(&spi->dev, "rate-1:%u\n", rate); + -+ if (rate > 4097) -+ return -EINVAL; -+ -+ if (rate < 2) -+ rate = 2; -+ + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER); + reg &= ~(0xfff << 16); + reg |= (rate - 2) << 16; @@ -446,15 +436,12 @@ + +static int mt7621_spi_setup(struct spi_device *spi) +{ -+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); ++ struct spi_master *master = spi->master; + -+ if ((spi->max_speed_hz == 0) || -+ (spi->max_speed_hz > (rs->sys_freq / 2))) -+ spi->max_speed_hz = (rs->sys_freq / 2); -+ -+ if (spi->max_speed_hz < (rs->sys_freq / 4097)) { -+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n", -+ spi->max_speed_hz); ++ if ((spi->max_speed_hz > master->max_speed_hz) || ++ (spi->max_speed_hz < master->min_speed_hz)) { ++ dev_err(&spi->dev, "invalide requested speed %d Hz\n", ++ spi->max_speed_hz); + return -EINVAL; + } + @@ -472,17 +459,14 @@ + const struct of_device_id *match; + struct spi_master *master; + struct mt7621_spi *rs; -+ unsigned long flags; + void __iomem *base; + struct resource *r; -+ int status = 0; + struct clk *clk; -+ struct mt7621_spi_ops *ops; ++ int ret; + + match = of_match_device(mt7621_spi_match, &pdev->dev); + if (!match) + return -EINVAL; -+ ops = (struct mt7621_spi_ops *)match->data; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, r); @@ -491,45 +475,57 @@ + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", -+ status); ++ dev_err(&pdev->dev, "unable to get SYS clock\n"); + return PTR_ERR(clk); + } + -+ status = clk_prepare_enable(clk); -+ if (status) -+ return status; ++ ret = clk_prepare_enable(clk); ++ if (ret) ++ goto err_clk; + + master = spi_alloc_master(&pdev->dev, sizeof(*rs)); + if (master == NULL) { -+ dev_info(&pdev->dev, "master allocation failed\n"); -+ return -ENOMEM; ++ dev_err(&pdev->dev, "master allocation failed\n"); ++ ret = -ENOMEM; ++ goto err_clk; + } + ++ master->dev.of_node = pdev->dev.of_node; + master->mode_bits = MT7621_SPI_MODE_BITS; -+ ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->min_speed_hz = clk_get_rate(clk) / 4097; ++ master->max_speed_hz = clk_get_rate(clk) / 2; ++ master->flags = SPI_MASTER_HALF_DUPLEX; + master->setup = mt7621_spi_setup; + master->transfer_one_message = mt7621_spi_transfer_one_message; -+ master->bits_per_word_mask = SPI_BPW_MASK(8); -+ master->dev.of_node = pdev->dev.of_node; + master->num_chipselect = 2; + + dev_set_drvdata(&pdev->dev, master); + + rs = spi_master_get_devdata(master); ++ rs->master = master; + rs->base = base; + rs->clk = clk; -+ rs->master = master; -+ rs->sys_freq = clk_get_rate(rs->clk); -+ rs->ops = ops; -+ dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); -+ spin_lock_irqsave(&rs->lock, flags); + + device_reset(&pdev->dev); + + mt7621_spi_reset(rs, 0); + -+ return spi_register_master(master); ++ ret = devm_spi_register_master(&pdev->dev, master); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "devm_spi_register_master error.\n"); ++ goto err_master; ++ } ++ ++ return ret; ++ ++err_master: ++ spi_master_put(master); ++ kfree(master); ++err_clk: ++ clk_disable_unprepare(clk); ++ ++ return ret; +} + +static int mt7621_spi_remove(struct platform_device *pdev) @@ -540,8 +536,7 @@ + master = dev_get_drvdata(&pdev->dev); + rs = spi_master_get_devdata(master); + -+ clk_disable(rs->clk); -+ spi_unregister_master(master); ++ clk_disable_unprepare(rs->clk); + + return 0; +}