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[140.113.45.114]) by smtp.gmail.com with ESMTPSA id ux7sm10833184pac.10.2015.10.10.20.54.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Oct 2015 20:54:43 -0700 (PDT) From: Michael Lee To: blogic@openwrt.org Date: Sun, 11 Oct 2015 11:54:27 +0800 Message-Id: <1444535674-3117-1-git-send-email-igvtee@gmail.com> X-Mailer: git-send-email 2.3.6 Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 1/8] ramips: complete mt7621 spi register define X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Signed-off-by: Michael Lee --- ...0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 113 ++++++++++++++++----- 1 file changed, 85 insertions(+), 28 deletions(-) diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch index 589c67e..a412cf4 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch @@ -1,6 +1,6 @@ --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -439,6 +439,12 @@ +@@ -439,6 +439,12 @@ config SPI_RT2880 help This selects a driver for the Ralink RT288x/RT305x SPI Controller. @@ -15,7 +15,7 @@ depends on ARCH_S3C24XX --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -46,6 +46,7 @@ +@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70l obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o --- /dev/null +++ b/drivers/spi/spi-mt7621.c -@@ -0,0 +1,480 @@ +@@ -0,0 +1,537 @@ +/* + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver + * @@ -56,34 +56,91 @@ + +#include + -+#define SPI_BPW_MASK(bits) BIT((bits) - 1) -+ +#define DRIVER_NAME "spi-mt7621" +/* in usec */ +#define RALINK_SPI_WAIT_MAX_LOOP 2000 + -+/* SPISTAT register bit field */ -+#define SPISTAT_BUSY BIT(0) -+ +#define MT7621_SPI_TRANS 0x00 -+#define SPITRANS_BUSY BIT(16) -+ +#define MT7621_SPI_OPCODE 0x04 +#define MT7621_SPI_DATA0 0x08 +#define MT7621_SPI_DATA4 0x18 -+#define SPI_CTL_TX_RX_CNT_MASK 0xff -+#define SPI_CTL_START BIT(8) -+ -+#define MT7621_SPI_POLAR 0x38 +#define MT7621_SPI_MASTER 0x28 +#define MT7621_SPI_MOREBUF 0x2c ++#define MT7621_SPI_QUEUE_CTL 0x30 ++#define MT7621_SPI_STATUS 0x34 ++#define MT7621_SPI_POLAR 0x38 +#define MT7621_SPI_SPACE 0x3c + -+#define MT7621_CPHA BIT(5) -+#define MT7621_CPOL BIT(4) -+#define MT7621_LSB_FIRST BIT(3) -+ -+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH) ++/* MT7621_SPI_TRANS */ ++#define SPITRANS_ADDREXT_MASK 0xff ++#define SPITRANS_ADDREXT_OFFSET 24 ++#define SPITRANS_ADDRSIZE_MASK 0x3 ++#define SPITRANS_ADDRSIZE_OFFSET 19 ++#define SPITRANS_BUSY BIT(16) ++#define SPITRANS_START BIT(8) ++#define SPITRANS_BYTECNT_MASK 0xf ++#define SPITRANS_MISO_OFFSET 4 ++#define SPITRANS_MOSI_OFFSET 0 ++ ++/* MT7621_SPI_OPCODE */ ++#define SPIOP_MB_OPCODE_OFFSET 24 ++#define SPIOP_MB_ADDR_MASK 0xffffff ++ ++/* MT7621_SPI_MASTER */ ++#define SPIMASTER_CS_MASK 0x7 ++#define SPIMASTER_CS_OFFSET 29 ++#define SPIMASTER_CLK_HIGH BIT(28) ++#define SPIMASTER_CLKSEL_MASK 0xfff ++#define SPIMASTER_CLKSEL_OFFSET 16 ++#define SPIMASTER_CSDSEL_MASK 0x1f ++#define SPIMASTER_CSDSEL_OFFSET 11 ++#define SPIMASTER_FULL_DUPLEX BIT(10) ++#define SPIMASTER_INTR_ENABLE BIT(9) ++#define SPIMASTER_START_6CLK BIT(8) ++#define SPIMASTER_PREFETCH_ENABLE BIT(7) ++#define SPIMASTER_BIDIR_MODE BIT(6) ++#define SPIMASTER_CPHA BIT(5) ++#define SPIMASTER_CPOL BIT(4) ++#define SPIMASTER_LSB BIT(3) ++#define SPIMASTER_MB_MODE BIT(2) ++#define SPIMASTER_SERIAL_MASK 0x3 ++ ++/* MT7621_SPI_MOREBUF */ ++#define SPIMB_CMD_MASK 0x3f ++#define SPIMB_CMD_OFFSET 24 ++#define SPIMB_MISO_MASK 0x1ff ++#define SPIMB_MISO_OFFSET 12 ++#define SPIMB_MOSI_MASK 0x1ff ++#define SPIMB_MOSI_OFFSET 0 ++ ++/* MT7621_SPI_QUEUE_CTL */ ++#define SPIQCTL_PAGE_MASK 0x3f ++#define SPIQCTL_PAGE_OFFSET 26 ++#define SPIQCTL_BUSY BIT(12) ++#define SPIQCTL_ADDRSIZE_MASK 0x3 ++#define SPIQCTL_ADDRSIZER_OFFSET 10 ++#define SPIQCTL_ADDRSIZE_OFFSET 8 ++#define SPIQCTL_MOSI_MASK 0xf ++#define SPIQCTL_FASTSEL_MASK 0x7 ++ ++/* MT7621_SPI_STATUS */ ++#define SPISTA_MODE_MASK 0x3 ++#define SPISTA_MODE_OFFSET 4 ++#define SPISTA_OK BIT(0) ++ ++/* MT7621_SPI_POLAR */ ++#define SPIPOL_CSPOL_MASK 0xff ++#define SPIPOL_CSPOL_OFFSET 0 ++#define SPIPOL_CSPOL_HIGH 1 ++ ++/* define MT7621_SPI_SPACE */ ++#define SPISPA_CS_MASK 0x7 ++#define SPISPA_CS_OFFSET 12 ++#define SPISPA_CLKSEL_MASK 0xfff ++#define SPISPA_CLKSEL_OFFSET 0 ++ ++#define MT7621_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \ ++ SPI_CS_HIGH) + +struct mt7621_spi; + @@ -161,22 +218,22 @@ + reg |= (rate - 2) << 16; + rs->speed = speed; + -+ reg &= ~MT7621_LSB_FIRST; ++ reg &= ~SPIMASTER_LSB; + if (spi->mode & SPI_LSB_FIRST) -+ reg |= MT7621_LSB_FIRST; ++ reg |= SPIMASTER_LSB; + -+ reg &= ~(MT7621_CPHA | MT7621_CPOL); ++ reg &= ~(SPIMASTER_CPHA | SPIMASTER_CPOL); + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + break; + case SPI_MODE_1: -+ reg |= MT7621_CPHA; ++ reg |= SPIMASTER_CPHA; + break; + case SPI_MODE_2: -+ reg |= MT7621_CPOL; ++ reg |= SPIMASTER_CPOL; + break; + case SPI_MODE_3: -+ reg |= MT7621_CPOL | MT7621_CPHA; ++ reg |= SPIMASTER_CPOL | SPIMASTER_CPHA; + break; + } + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg); @@ -261,7 +318,7 @@ + mt7621_spi_set_cs(spi, 1); + + val = mt7621_spi_read(rs, MT7621_SPI_TRANS); -+ val |= SPI_CTL_START; ++ val |= SPITRANS_START; + mt7621_spi_write(rs, MT7621_SPI_TRANS, val); + + mt7621_spi_wait_till_ready(spi); @@ -346,7 +403,7 @@ + mt7621_spi_set_cs(spi, 1); + + val = mt7621_spi_read(rs, MT7621_SPI_TRANS); -+ val |= SPI_CTL_START; ++ val |= SPITRANS_START; + mt7621_spi_write(rs, MT7621_SPI_TRANS, val); + + mt7621_spi_wait_till_ready(spi); @@ -449,7 +506,7 @@ + return -ENOMEM; + } + -+ master->mode_bits = RT2880_SPI_MODE_BITS; ++ master->mode_bits = MT7621_SPI_MODE_BITS; + + master->setup = mt7621_spi_setup; + master->transfer_one_message = mt7621_spi_transfer_one_message;