From patchwork Thu Oct 8 14:16:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingyu Li X-Patchwork-Id: 527735 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BDAA3140D93 for ; Fri, 9 Oct 2015 01:21:08 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=qsiMQVPm; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 5C3C728C783; Thu, 8 Oct 2015 16:16:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 3E57828C738 for ; Thu, 8 Oct 2015 16:15:07 +0200 (CEST) X-policyd-weight: using cached result; rate:hard: -8.5 Received: from mail-pa0-f45.google.com (mail-pa0-f45.google.com [209.85.220.45]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 8 Oct 2015 16:14:55 +0200 (CEST) Received: by pacex6 with SMTP id ex6so56478717pac.0 for ; Thu, 08 Oct 2015 07:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=73gQYBeA8ltLNSy7cm8VxnS7kR+cyIWpSmJONUaXUjQ=; b=qsiMQVPmUQUFTwKoclC/H/unvcDNKILV06V58kLC5FenAYU5pmSPLnc5CcW54Qqfe2 Khs/C6r11ySfHol6UV3Iolh3JNRQMf2NQnuQRUMN99ctWFhvHlAM8AMD1d7EILknH5tG wfCE2GOrpCT0KOlfp4zdRsDix5JuozD6tLkw+k+gRsL5u0Yu4BjaPAyJqZyQJKpW3Z7b R5ssPpnsC61heR22gXK8vR/3PI4eXuD27l2HEdix5GaKxxeQ9KUJWpQoXgaw3ycquJ9i p8QDSApZ5L5+FuHb+i3N+rpsm06tE8R+gBk2ZPxjuebDcbjwv0drLHAI1A9GfzFVIXQD sGeg== X-Received: by 10.68.65.13 with SMTP id t13mr8464103pbs.43.1444313781278; Thu, 08 Oct 2015 07:16:21 -0700 (PDT) Received: from localhost.localdomain (f45hc114.RAS.nctu.edu.tw. [140.113.45.114]) by smtp.gmail.com with ESMTPSA id hq8sm46122436pad.35.2015.10.08.07.16.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Oct 2015 07:16:20 -0700 (PDT) From: Michael Lee To: blogic@openwrt.org Date: Thu, 8 Oct 2015 22:16:05 +0800 Message-Id: <1444313768-23970-5-git-send-email-igvtee@gmail.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1444313768-23970-1-git-send-email-igvtee@gmail.com> References: <1444313768-23970-1-git-send-email-igvtee@gmail.com> Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 5/8] ramips: improve rt2880 spi setup X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" * check clock rate, SPI mode, and word sizes * setup spi polarity * enable spi1 hw if need Signed-off-by: Michael Lee --- ...0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch | 73 ++++++++++++++++++---- 1 file changed, 62 insertions(+), 11 deletions(-) diff --git a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch index 605bda9..418a094 100644 --- a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch @@ -41,7 +41,7 @@ Acked-by: John Crispin spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o --- /dev/null +++ b/drivers/spi/spi-rt2880.c -@@ -0,0 +1,488 @@ +@@ -0,0 +1,539 @@ +/* + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver + * @@ -175,6 +175,7 @@ Acked-by: John Crispin + unsigned int sys_freq; + unsigned int speed; + u16 wait_loops; ++ u16 mode; + struct clk *clk; +}; + @@ -265,6 +266,17 @@ Acked-by: John Crispin + return 0; +} + ++static u32 get_arbiter_offset(struct spi_master *master) ++{ ++ u32 offset; ++ ++ offset = RAMIPS_SPI_ARBITER; ++ if (master->bus_num == 1) ++ offset -= RAMIPS_SPI_DEV_OFFSET; ++ ++ return offset; ++} ++ +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable) +{ + if (enable) @@ -396,21 +408,60 @@ Acked-by: John Crispin + +static int rt2880_spi_setup(struct spi_device *spi) +{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); ++ struct spi_master *master = spi->master; ++ struct rt2880_spi *rs = spi_master_get_devdata(master); ++ u32 reg, old_reg, arbit_off; + -+ if ((spi->max_speed_hz == 0) || -+ (spi->max_speed_hz > (rs->sys_freq / 2))) -+ spi->max_speed_hz = (rs->sys_freq / 2); ++ if ((spi->max_speed_hz > master->max_speed_hz) || ++ (spi->max_speed_hz < master->min_speed_hz)) { ++ dev_err(&spi->dev, "invalide requested speed %d Hz\n", ++ spi->max_speed_hz); ++ return -EINVAL; ++ } + -+ if (spi->max_speed_hz < (rs->sys_freq / 128)) { -+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n", -+ spi->max_speed_hz); ++ if (!(master->bits_per_word_mask & ++ BIT(spi->bits_per_word - 1))) { ++ dev_err(&spi->dev, "invalide bits_per_word %d\n", ++ spi->bits_per_word); + return -EINVAL; + } + -+ /* -+ * baudrate & width will be set rt2880_spi_setup_transfer -+ */ ++ /* the hardware seems can't work on mode0 force it to mode3 */ ++ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) { ++ dev_warn(&spi->dev, "force spi mode3\n"); ++ spi->mode |= SPI_MODE_3; ++ } ++ ++ /* chip polarity */ ++ arbit_off = get_arbiter_offset(master); ++ reg = old_reg = rt2880_spi_read(rs, arbit_off); ++ if (spi->mode & SPI_CS_HIGH) { ++ switch (master->bus_num) { ++ case 1: ++ reg |= SPI1_POR; ++ break; ++ default: ++ reg |= SPI0_POR; ++ break; ++ } ++ } else { ++ switch (master->bus_num) { ++ case 1: ++ reg &= ~SPI1_POR; ++ break; ++ default: ++ reg &= ~SPI0_POR; ++ break; ++ } ++ } ++ ++ /* enable spi1 */ ++ if (master->bus_num == 1) ++ reg |= SPICTL_ARB_EN; ++ ++ if (reg != old_reg) ++ rt2880_spi_write(rs, arbit_off, reg); ++ + return 0; +} +