From patchwork Thu Oct 8 14:16:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingyu Li X-Patchwork-Id: 527733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 82611140DA3 for ; Fri, 9 Oct 2015 01:20:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=nq44OScK; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 9D84E28C75F; Thu, 8 Oct 2015 16:16:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id ED2EE28C72F for ; Thu, 8 Oct 2015 16:15:03 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-pa0-f47.google.com (mail-pa0-f47.google.com [209.85.220.47]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 8 Oct 2015 16:14:55 +0200 (CEST) Received: by padhy16 with SMTP id hy16so56307753pad.1 for ; Thu, 08 Oct 2015 07:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fzRj+jh2OMo93WDzR10JxUtnj0oVxSUSQV2z84kfgoA=; b=nq44OScKPi++1GM/P6KrGwEctYXsC8uTL+HkMSq/z2DT8jrZWrFQxkxovHfA5+4Rnh 58HeaYWBSIODVYTFak6PmLbSM2HTfnoqQJ52z35Xr/WEHI3DbpRDV3fdlqH4zzoKXFxZ CXfmqs22kjtAlsXTNWc3Oq8FKfoq6lWgjSDiaOh0+JpFgGsCKWQEpQQqI/3iJui2OmtK DUBuDIU1ANB65F41gzw4Y/mGChkElcTCTQgSLVwyvuS8LRX9wyMYE0gHCR6KwJ3feXyW FNU2HiQW5Ra7ZJ4H2CVLwDxSANEU5f+mk6ym5VgNOm0r6fuJa5CZN+1PwLgDvVgLtXrX AF6w== X-Received: by 10.68.243.99 with SMTP id wx3mr8376455pbc.33.1444313780075; Thu, 08 Oct 2015 07:16:20 -0700 (PDT) Received: from localhost.localdomain (f45hc114.RAS.nctu.edu.tw. [140.113.45.114]) by smtp.gmail.com with ESMTPSA id hq8sm46122436pad.35.2015.10.08.07.16.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Oct 2015 07:16:19 -0700 (PDT) From: Michael Lee To: blogic@openwrt.org Date: Thu, 8 Oct 2015 22:16:04 +0800 Message-Id: <1444313768-23970-4-git-send-email-igvtee@gmail.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1444313768-23970-1-git-send-email-igvtee@gmail.com> References: <1444313768-23970-1-git-send-email-igvtee@gmail.com> Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 4/8] ramips: clean up rt2880 spi probe/remove X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" * fill struct according to the member order * add error clean up * set min/max spi speed. so we don't need to check again Signed-off-by: Michael Lee --- ...0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch | 59 +++++++++++++--------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch index 00fdeed..605bda9 100644 --- a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch @@ -41,7 +41,7 @@ Acked-by: John Crispin spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o --- /dev/null +++ b/drivers/spi/spi-rt2880.c -@@ -0,0 +1,479 @@ +@@ -0,0 +1,488 @@ +/* + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver + * @@ -166,6 +166,9 @@ Acked-by: John Crispin +#define SPI1_POR BIT(1) +#define SPI0_POR BIT(0) + ++#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \ ++ SPI_CS_HIGH) ++ +struct rt2880_spi { + struct spi_master *master; + void __iomem *base; @@ -223,13 +226,6 @@ Acked-by: John Crispin + rate = roundup_pow_of_two(rate); + dev_dbg(&spi->dev, "rate-2:%u\n", rate); + -+ /* check if requested speed is too small */ -+ if (rate > 128) -+ return -EINVAL; -+ -+ if (rate < 2) -+ rate = 2; -+ + /* Convert the rate to SPI clock divisor value. */ + prescale = ilog2(rate / 2); + dev_dbg(&spi->dev, "prescale:%u\n", prescale); @@ -430,11 +426,10 @@ Acked-by: John Crispin +{ + struct spi_master *master; + struct rt2880_spi *rs; -+ unsigned long flags; + void __iomem *base; + struct resource *r; -+ int status = 0; + struct clk *clk; ++ int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, r); @@ -443,36 +438,37 @@ Acked-by: John Crispin + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", -+ status); ++ dev_err(&pdev->dev, "unable to get SYS clock\n"); + return PTR_ERR(clk); + } + -+ status = clk_prepare_enable(clk); -+ if (status) -+ return status; ++ ret = clk_prepare_enable(clk); ++ if (ret) ++ goto err_clk; + + master = spi_alloc_master(&pdev->dev, sizeof(*rs)); + if (master == NULL) { + dev_dbg(&pdev->dev, "master allocation failed\n"); -+ return -ENOMEM; ++ ret = -ENOMEM; ++ goto err_clk; + } + -+ /* we support only mode 0, and no options */ -+ master->mode_bits = 0; -+ ++ master->dev.of_node = pdev->dev.of_node; ++ master->mode_bits = RT2880_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->min_speed_hz = clk_get_rate(clk) / 128; ++ master->max_speed_hz = clk_get_rate(clk) / 2; ++ master->flags = SPI_MASTER_HALF_DUPLEX; + master->setup = rt2880_spi_setup; + master->transfer_one_message = rt2880_spi_transfer_one_message; + master->num_chipselect = RALINK_NUM_CHIPSELECTS; -+ master->bits_per_word_mask = SPI_BPW_MASK(8); -+ master->dev.of_node = pdev->dev.of_node; + + dev_set_drvdata(&pdev->dev, master); + + rs = spi_master_get_devdata(master); ++ rs->master = master; + rs->base = base; + rs->clk = clk; -+ rs->master = master; + rs->sys_freq = clk_get_rate(rs->clk); + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); + @@ -480,7 +476,21 @@ Acked-by: John Crispin + + rt2880_spi_reset(rs); + -+ return spi_register_master(master); ++ ret = devm_spi_register_master(&pdev->dev, master); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "devm_spi_register_master error.\n"); ++ goto err_master; ++ } ++ ++ return ret; ++ ++err_master: ++ spi_master_put(master); ++ kfree(master); ++err_clk: ++ clk_disable_unprepare(clk); ++ ++ return ret; +} + +static int rt2880_spi_remove(struct platform_device *pdev) @@ -491,8 +501,7 @@ Acked-by: John Crispin + master = dev_get_drvdata(&pdev->dev); + rs = spi_master_get_devdata(master); + -+ clk_disable(rs->clk); -+ spi_unregister_master(master); ++ clk_disable_unprepare(rs->clk); + + return 0; +}