From patchwork Tue Sep 1 12:14:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yousong Zhou X-Patchwork-Id: 512800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6E53F14056B for ; Tue, 1 Sep 2015 22:22:13 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=DZcipdl9; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 1924D28C659; Tue, 1 Sep 2015 14:18:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id B633E28C167 for ; Tue, 1 Sep 2015 14:17:48 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Tue, 1 Sep 2015 14:17:46 +0200 (CEST) Received: by paczk9 with SMTP id zk9so27609789pac.0 for ; Tue, 01 Sep 2015 05:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X3wShcHkULJFrjwM/At7BdmxfBVdiXsVUef5d5mz9dA=; b=DZcipdl9vbCaAFQa1mw58DaHYLtjjr7JrU+ek5s0V0jmlXkYytAnYgEWWE3ygNaiEv vStnfMqdsy47uMsMGBYkJfN+I4NTiuIEFJvSinYTiYJLur92P1o8WUAwxJsmPZ9YVckT 8iDKCKvM7ygS78NNyWEJaruseICVR6yK+F34QSlPLwZlI38r0zMJQ9OgjexjJbb4/xsI hY1gscLOQKMwe3eml28Z6e2Namd2TYpuRfevHgzRhASecJxs6Q6C+fTVv1vfypEfK+LO ofKiA0bpby5Maii1PPOBz72j0V3skaO2x7vIuJlbTk/Ecdp04GCBr4TNkLMHlVE19Td/ MaYw== X-Received: by 10.69.26.161 with SMTP id iz1mr46609298pbd.17.1441109920871; Tue, 01 Sep 2015 05:18:40 -0700 (PDT) Received: from debian.corp.sankuai.com ([103.29.140.57]) by smtp.gmail.com with ESMTPSA id qc2sm17967378pbc.79.2015.09.01.05.18.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Sep 2015 05:18:40 -0700 (PDT) From: Yousong Zhou To: openwrt-devel@lists.openwrt.org Date: Tue, 1 Sep 2015 20:14:44 +0800 Message-Id: <1441109686-27796-4-git-send-email-yszhou4tech@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1441109686-27796-1-git-send-email-yszhou4tech@gmail.com> References: <1441109686-27796-1-git-send-email-yszhou4tech@gmail.com> Subject: [OpenWrt-Devel] [PATCH 4/6] generic: fix unrecognized opcode wsbh when building for MIPS16. X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" The issue was found and reported by hynman [1] when compiling reaver for ar71xx (Big Endian MIPS). {standard input}: Assembler messages: {standard input}:79: Error: unrecognized opcode `wsbh $2,$2' {standard input}:90: Error: unrecognized opcode `wsbh $3,$17' {standard input}:208: Error: unrecognized opcode `wsbh $2,$2' make[3]: *** [builder.o] Error 1 [1] https://github.com/openwrt/packages/commit/1e29676a8ac74f797f8ca799364681cec575ae6f#commitcomment-12901931 Signed-off-by: Yousong Zhou --- ...recognized-opcode-WSBH-DSBH-DSHD-when-usi.patch | 85 ++++++++++++++++++++ ...recognized-opcode-WSBH-DSBH-DSHD-when-usi.patch | 85 ++++++++++++++++++++ ...recognized-opcode-WSBH-DSBH-DSHD-when-usi.patch | 85 ++++++++++++++++++++ 3 files changed, 255 insertions(+) create mode 100644 target/linux/generic/patches-3.18/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch create mode 100644 target/linux/generic/patches-4.0/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch create mode 100644 target/linux/generic/patches-4.1/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch diff --git a/target/linux/generic/patches-3.18/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch b/target/linux/generic/patches-3.18/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch new file mode 100644 index 0000000..2056735 --- /dev/null +++ b/target/linux/generic/patches-3.18/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch @@ -0,0 +1,85 @@ +From f4b20c49109045fc2f58f7b67160f07ebd7f0ea7 Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Thu, 27 Aug 2015 09:58:53 +0800 +Subject: [PATCH] MIPS: Fix unrecognized opcode WSBH/DSBH/DSHD when using + MIPS16. + +The nomips16 has to be added both as function attribute and assembler +directive. + +When only function attribute was specified, the compiler will inline the +function when -Os optimization was applied. The generated assembly code +was cannot be correctly assembled because ISA mode switch has to be done +with a jump. + +When only ".set nomips" directive was used, the compiled function code +will be invalid because mixed MIPS16 and MIPS32 instructions were +generated by gcc. The result will be like the following, + + 00403100 <__arch_swab16>: + 403100: 7c0410a0 wsbh v0,a0 + 403104: e820ea31 swc2 $0,-5583(at) + +while correct code should be + + 00402650 <__arch_swab16>: + 402650: 7c0410a0 wsbh v0,a0 + 402654: 03e00008 jr ra + 402658: 3042ffff andi v0,v0,0xffff + +Signed-off-by: Yousong Zhou +--- + arch/mips/include/uapi/asm/swab.h | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h +index 8f2d184..4b1044d 100644 +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -16,11 +16,14 @@ + #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ + defined(_MIPS_ARCH_LOONGSON3A) + +-static inline __attribute_const__ __u16 __arch_swab16(__u16 x) ++#define __nomips16 __attribute__((nomips16)) ++ ++static inline __nomips16 __attribute_const__ __u16 __arch_swab16(__u16 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " .set pop \n" + : "=r" (x) +@@ -30,11 +33,12 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + } + #define __arch_swab16 __arch_swab16 + +-static inline __attribute_const__ __u32 __arch_swab32(__u32 x) ++static inline __nomips16 __attribute_const__ __u32 __arch_swab32(__u32 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + " .set pop \n" +@@ -50,11 +54,12 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) + * 64-bit kernel on r2 CPUs. + */ + #ifdef __mips64 +-static inline __attribute_const__ __u64 __arch_swab64(__u64 x) ++static inline __nomips16 __attribute_const__ __u64 __arch_swab64(__u64 x) + { + __asm__( + " .set push \n" + " .set arch=mips64r2 \n" ++ " .set nomips16 \n" + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " .set pop \n" +-- +1.7.10.4 + diff --git a/target/linux/generic/patches-4.0/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch b/target/linux/generic/patches-4.0/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch new file mode 100644 index 0000000..2056735 --- /dev/null +++ b/target/linux/generic/patches-4.0/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch @@ -0,0 +1,85 @@ +From f4b20c49109045fc2f58f7b67160f07ebd7f0ea7 Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Thu, 27 Aug 2015 09:58:53 +0800 +Subject: [PATCH] MIPS: Fix unrecognized opcode WSBH/DSBH/DSHD when using + MIPS16. + +The nomips16 has to be added both as function attribute and assembler +directive. + +When only function attribute was specified, the compiler will inline the +function when -Os optimization was applied. The generated assembly code +was cannot be correctly assembled because ISA mode switch has to be done +with a jump. + +When only ".set nomips" directive was used, the compiled function code +will be invalid because mixed MIPS16 and MIPS32 instructions were +generated by gcc. The result will be like the following, + + 00403100 <__arch_swab16>: + 403100: 7c0410a0 wsbh v0,a0 + 403104: e820ea31 swc2 $0,-5583(at) + +while correct code should be + + 00402650 <__arch_swab16>: + 402650: 7c0410a0 wsbh v0,a0 + 402654: 03e00008 jr ra + 402658: 3042ffff andi v0,v0,0xffff + +Signed-off-by: Yousong Zhou +--- + arch/mips/include/uapi/asm/swab.h | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h +index 8f2d184..4b1044d 100644 +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -16,11 +16,14 @@ + #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ + defined(_MIPS_ARCH_LOONGSON3A) + +-static inline __attribute_const__ __u16 __arch_swab16(__u16 x) ++#define __nomips16 __attribute__((nomips16)) ++ ++static inline __nomips16 __attribute_const__ __u16 __arch_swab16(__u16 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " .set pop \n" + : "=r" (x) +@@ -30,11 +33,12 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + } + #define __arch_swab16 __arch_swab16 + +-static inline __attribute_const__ __u32 __arch_swab32(__u32 x) ++static inline __nomips16 __attribute_const__ __u32 __arch_swab32(__u32 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + " .set pop \n" +@@ -50,11 +54,12 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) + * 64-bit kernel on r2 CPUs. + */ + #ifdef __mips64 +-static inline __attribute_const__ __u64 __arch_swab64(__u64 x) ++static inline __nomips16 __attribute_const__ __u64 __arch_swab64(__u64 x) + { + __asm__( + " .set push \n" + " .set arch=mips64r2 \n" ++ " .set nomips16 \n" + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " .set pop \n" +-- +1.7.10.4 + diff --git a/target/linux/generic/patches-4.1/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch b/target/linux/generic/patches-4.1/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch new file mode 100644 index 0000000..2056735 --- /dev/null +++ b/target/linux/generic/patches-4.1/133-MIPS-Fix-unrecognized-opcode-WSBH-DSBH-DSHD-when-usi.patch @@ -0,0 +1,85 @@ +From f4b20c49109045fc2f58f7b67160f07ebd7f0ea7 Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Thu, 27 Aug 2015 09:58:53 +0800 +Subject: [PATCH] MIPS: Fix unrecognized opcode WSBH/DSBH/DSHD when using + MIPS16. + +The nomips16 has to be added both as function attribute and assembler +directive. + +When only function attribute was specified, the compiler will inline the +function when -Os optimization was applied. The generated assembly code +was cannot be correctly assembled because ISA mode switch has to be done +with a jump. + +When only ".set nomips" directive was used, the compiled function code +will be invalid because mixed MIPS16 and MIPS32 instructions were +generated by gcc. The result will be like the following, + + 00403100 <__arch_swab16>: + 403100: 7c0410a0 wsbh v0,a0 + 403104: e820ea31 swc2 $0,-5583(at) + +while correct code should be + + 00402650 <__arch_swab16>: + 402650: 7c0410a0 wsbh v0,a0 + 402654: 03e00008 jr ra + 402658: 3042ffff andi v0,v0,0xffff + +Signed-off-by: Yousong Zhou +--- + arch/mips/include/uapi/asm/swab.h | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h +index 8f2d184..4b1044d 100644 +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -16,11 +16,14 @@ + #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ + defined(_MIPS_ARCH_LOONGSON3A) + +-static inline __attribute_const__ __u16 __arch_swab16(__u16 x) ++#define __nomips16 __attribute__((nomips16)) ++ ++static inline __nomips16 __attribute_const__ __u16 __arch_swab16(__u16 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " .set pop \n" + : "=r" (x) +@@ -30,11 +33,12 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + } + #define __arch_swab16 __arch_swab16 + +-static inline __attribute_const__ __u32 __arch_swab32(__u32 x) ++static inline __nomips16 __attribute_const__ __u32 __arch_swab32(__u32 x) + { + __asm__( + " .set push \n" + " .set arch=mips32r2 \n" ++ " .set nomips16 \n" + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + " .set pop \n" +@@ -50,11 +54,12 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) + * 64-bit kernel on r2 CPUs. + */ + #ifdef __mips64 +-static inline __attribute_const__ __u64 __arch_swab64(__u64 x) ++static inline __nomips16 __attribute_const__ __u64 __arch_swab64(__u64 x) + { + __asm__( + " .set push \n" + " .set arch=mips64r2 \n" ++ " .set nomips16 \n" + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " .set pop \n" +-- +1.7.10.4 +