From patchwork Thu Aug 13 02:37:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Olivari X-Patchwork-Id: 506820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 119221401F6 for ; Thu, 13 Aug 2015 12:39:47 +1000 (AEST) Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id AA85828BF85; Thu, 13 Aug 2015 04:38:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id D1B4528003F for ; Thu, 13 Aug 2015 04:37:12 +0200 (CEST) X-policyd-weight: using cached result; rate:hard: -7.6 Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 13 Aug 2015 04:37:12 +0200 (CEST) Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 99672140D5A; Thu, 13 Aug 2015 02:37:54 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 8C4E0140D6A; Thu, 13 Aug 2015 02:37:54 +0000 (UTC) Received: from mathieu-linux.qualcomm.com (qf-scl1nat.qualcomm.com [207.114.132.30]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mathieu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D4521140D5A; Thu, 13 Aug 2015 02:37:50 +0000 (UTC) From: Mathieu Olivari To: nbd@openwrt.org, jogo@openwrt.org, blogic@openwrt.org Date: Wed, 12 Aug 2015 19:37:41 -0700 Message-Id: <1439433464-1526-3-git-send-email-mathieu@codeaurora.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439433464-1526-1-git-send-email-mathieu@codeaurora.org> References: <1439433464-1526-1-git-send-email-mathieu@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 2/5] ipq806x: add hwspinlock support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" This change cherry-picks the following 3 changes from linux-next: *fb7737 hwspinlock/core: add device tree support *19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block *bd5717 hwspinlock: qcom: Correct msb in regmap_field We're also adding a patch to add the hardware spinlock device nodes on IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch). Signed-off-by: Mathieu Olivari --- ...0-hwspinlock-core-add-device-tree-support.patch | 167 +++++++++++++++ ...qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch | 234 +++++++++++++++++++++ ...spinlock-qcom-Correct-msb-in-regmap_field.patch | 26 +++ ...3-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch | 20 ++ ...1-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch | 6 +- ...-qcom-add-pcie-nodes-to-ipq806x-platforms.patch | 4 +- .../patches-3.18/115-add-pcie-aux-clk-dts.patch | 6 +- .../157-ARM-DT-ipq8064-Add-ADM-device-node.patch | 2 +- ...-dts-Add-NAND-controller-node-for-ipq806x.patch | 2 +- ...-qcom-add-gmac-nodes-to-ipq806x-platforms.patch | 2 +- ...0-hwspinlock-core-add-device-tree-support.patch | 167 +++++++++++++++ ...qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch | 234 +++++++++++++++++++++ ...spinlock-qcom-Correct-msb-in-regmap_field.patch | 26 +++ ...3-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch | 21 ++ ...-qcom-add-pcie-nodes-to-ipq806x-platforms.patch | 2 +- .../patches-4.1/115-add-pcie-aux-clk-dts.patch | 6 +- .../patches-4.1/126-add-rpm-to-ipq8064-dts.patch | 4 +- ...m-Add-necessary-DT-data-for-Krait-cpufreq.patch | 4 +- .../157-ARM-DT-ipq8064-Add-ADM-device-node.patch | 2 +- ...-dts-Add-NAND-controller-node-for-ipq806x.patch | 2 +- ...-qcom-add-gmac-nodes-to-ipq806x-platforms.patch | 2 +- 21 files changed, 917 insertions(+), 22 deletions(-) create mode 100644 target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch create mode 100644 target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch create mode 100644 target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch create mode 100644 target/linux/ipq806x/patches-3.18/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch create mode 100644 target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch create mode 100644 target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch create mode 100644 target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch create mode 100644 target/linux/ipq806x/patches-4.1/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch diff --git a/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch b/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch new file mode 100644 index 0000000..04f35b7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch @@ -0,0 +1,167 @@ +From fb7737e949e31d8a71acee6bbb670f32dbd2a2c0 Mon Sep 17 00:00:00 2001 +From: Suman Anna +Date: Wed, 4 Mar 2015 20:01:14 -0600 +Subject: [PATCH] hwspinlock/core: add device tree support + +This patch adds a new OF-friendly API of_hwspin_lock_get_id() +for hwspinlock clients to use/request locks from a hwspinlock +device instantiated through a device-tree blob. This new API +can be used by hwspinlock clients to get the id for a specific +lock using the phandle + args specifier, so that it can be +requested using the available hwspin_lock_request_specific() +API. + +Signed-off-by: Suman Anna +Reviewed-by: Bjorn Andersson +[small comment clarification] +Signed-off-by: Ohad Ben-Cohen +--- + Documentation/hwspinlock.txt | 10 +++++ + drivers/hwspinlock/hwspinlock_core.c | 79 ++++++++++++++++++++++++++++++++++++ + include/linux/hwspinlock.h | 7 ++++ + 3 files changed, 96 insertions(+) + +--- a/Documentation/hwspinlock.txt ++++ b/Documentation/hwspinlock.txt +@@ -48,6 +48,16 @@ independent, drivers. + ids for predefined purposes. + Should be called from a process context (might sleep). + ++ int of_hwspin_lock_get_id(struct device_node *np, int index); ++ - retrieve the global lock id for an OF phandle-based specific lock. ++ This function provides a means for DT users of a hwspinlock module ++ to get the global lock id of a specific hwspinlock, so that it can ++ be requested using the normal hwspin_lock_request_specific() API. ++ The function returns a lock id number on success, -EPROBE_DEFER if ++ the hwspinlock device is not yet registered with the core, or other ++ error values. ++ Should be called from a process context (might sleep). ++ + int hwspin_lock_free(struct hwspinlock *hwlock); + - free a previously-assigned hwspinlock; returns 0 on success, or an + appropriate error code on failure (e.g. -EINVAL if the hwspinlock +--- a/drivers/hwspinlock/hwspinlock_core.c ++++ b/drivers/hwspinlock/hwspinlock_core.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "hwspinlock_internal.h" + +@@ -257,6 +258,84 @@ void __hwspin_unlock(struct hwspinlock * + } + EXPORT_SYMBOL_GPL(__hwspin_unlock); + ++/** ++ * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id ++ * @bank: the hwspinlock device bank ++ * @hwlock_spec: hwlock specifier as found in the device tree ++ * ++ * This is a simple translation function, suitable for hwspinlock platform ++ * drivers that only has a lock specifier length of 1. ++ * ++ * Returns a relative index of the lock within a specified bank on success, ++ * or -EINVAL on invalid specifier cell count. ++ */ ++static inline int ++of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) ++{ ++ if (WARN_ON(hwlock_spec->args_count != 1)) ++ return -EINVAL; ++ ++ return hwlock_spec->args[0]; ++} ++ ++/** ++ * of_hwspin_lock_get_id() - get lock id for an OF phandle-based specific lock ++ * @np: device node from which to request the specific hwlock ++ * @index: index of the hwlock in the list of values ++ * ++ * This function provides a means for DT users of the hwspinlock module to ++ * get the global lock id of a specific hwspinlock using the phandle of the ++ * hwspinlock device, so that it can be requested using the normal ++ * hwspin_lock_request_specific() API. ++ * ++ * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock ++ * device is not yet registered, -EINVAL on invalid args specifier value or an ++ * appropriate error as returned from the OF parsing of the DT client node. ++ */ ++int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ struct of_phandle_args args; ++ struct hwspinlock *hwlock; ++ struct radix_tree_iter iter; ++ void **slot; ++ int id; ++ int ret; ++ ++ ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, ++ &args); ++ if (ret) ++ return ret; ++ ++ /* Find the hwspinlock device: we need its base_id */ ++ ret = -EPROBE_DEFER; ++ rcu_read_lock(); ++ radix_tree_for_each_slot(slot, &hwspinlock_tree, &iter, 0) { ++ hwlock = radix_tree_deref_slot(slot); ++ if (unlikely(!hwlock)) ++ continue; ++ ++ if (hwlock->bank->dev->of_node == args.np) { ++ ret = 0; ++ break; ++ } ++ } ++ rcu_read_unlock(); ++ if (ret < 0) ++ goto out; ++ ++ id = of_hwspin_lock_simple_xlate(&args); ++ if (id < 0 || id >= hwlock->bank->num_locks) { ++ ret = -EINVAL; ++ goto out; ++ } ++ id += hwlock->bank->base_id; ++ ++out: ++ of_node_put(args.np); ++ return ret ? ret : id; ++} ++EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id); ++ + static int hwspin_lock_register_single(struct hwspinlock *hwlock, int id) + { + struct hwspinlock *tmp; +--- a/include/linux/hwspinlock.h ++++ b/include/linux/hwspinlock.h +@@ -26,6 +26,7 @@ + #define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ + + struct device; ++struct device_node; + struct hwspinlock; + struct hwspinlock_device; + struct hwspinlock_ops; +@@ -66,6 +67,7 @@ int hwspin_lock_unregister(struct hwspin + struct hwspinlock *hwspin_lock_request(void); + struct hwspinlock *hwspin_lock_request_specific(unsigned int id); + int hwspin_lock_free(struct hwspinlock *hwlock); ++int of_hwspin_lock_get_id(struct device_node *np, int index); + int hwspin_lock_get_id(struct hwspinlock *hwlock); + int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, + unsigned long *); +@@ -120,6 +122,11 @@ void __hwspin_unlock(struct hwspinlock * + { + } + ++static inline int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ return 0; ++} ++ + static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) + { + return 0; diff --git a/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch b/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch new file mode 100644 index 0000000..581b199 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch @@ -0,0 +1,234 @@ +From 19a0f61224d2d91860fa8291ab63cb104ee86bdd Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Tue, 24 Mar 2015 10:11:05 -0700 +Subject: [PATCH] hwspinlock: qcom: Add support for Qualcomm HW Mutex block + +Add driver for Qualcomm Hardware Mutex block found in many Qualcomm +SoCs. + +Based on initial effort by Kumar Gala + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Reviewed-by: Jeffrey Hugo +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/Kconfig | 12 +++ + drivers/hwspinlock/Makefile | 1 + + drivers/hwspinlock/qcom_hwspinlock.c | 181 +++++++++++++++++++++++++++++++++++ + 3 files changed, 194 insertions(+) + create mode 100644 drivers/hwspinlock/qcom_hwspinlock.c + +--- a/drivers/hwspinlock/Kconfig ++++ b/drivers/hwspinlock/Kconfig +@@ -18,6 +18,18 @@ config HWSPINLOCK_OMAP + + If unsure, say N. + ++config HWSPINLOCK_QCOM ++ tristate "Qualcomm Hardware Spinlock device" ++ depends on ARCH_QCOM ++ select HWSPINLOCK ++ select MFD_SYSCON ++ help ++ Say y here to support the Qualcomm Hardware Mutex functionality, which ++ provides a synchronisation mechanism for the various processors on ++ the SoC. ++ ++ If unsure, say N. ++ + config HSEM_U8500 + tristate "STE Hardware Semaphore functionality" + depends on ARCH_U8500 +--- a/drivers/hwspinlock/Makefile ++++ b/drivers/hwspinlock/Makefile +@@ -4,4 +4,5 @@ + + obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o + obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o ++obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o + obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +--- /dev/null ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2015, Sony Mobile Communications AB ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++#define QCOM_MUTEX_APPS_PROC_ID 1 ++#define QCOM_MUTEX_NUM_LOCKS 32 ++ ++static int qcom_hwspinlock_trylock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) ++ return ret; ++ ++ return lock_owner == QCOM_MUTEX_APPS_PROC_ID; ++} ++ ++static void qcom_hwspinlock_unlock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) { ++ pr_err("%s: unable to query spinlock owner\n", __func__); ++ return; ++ } ++ ++ if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) { ++ pr_err("%s: spinlock not owned by us (actual owner is %d)\n", ++ __func__, lock_owner); ++ } ++ ++ ret = regmap_field_write(field, 0); ++ if (ret) ++ pr_err("%s: failed to unlock spinlock\n", __func__); ++} ++ ++static const struct hwspinlock_ops qcom_hwspinlock_ops = { ++ .trylock = qcom_hwspinlock_trylock, ++ .unlock = qcom_hwspinlock_unlock, ++}; ++ ++static const struct of_device_id qcom_hwspinlock_of_match[] = { ++ { .compatible = "qcom,sfpb-mutex" }, ++ { .compatible = "qcom,tcsr-mutex" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); ++ ++static int qcom_hwspinlock_probe(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank; ++ struct device_node *syscon; ++ struct reg_field field; ++ struct regmap *regmap; ++ size_t array_size; ++ u32 stride; ++ u32 base; ++ int ret; ++ int i; ++ ++ syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); ++ if (!syscon) { ++ dev_err(&pdev->dev, "no syscon property\n"); ++ return -ENODEV; ++ } ++ ++ regmap = syscon_node_to_regmap(syscon); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no offset in syscon\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no stride syscon\n"); ++ return -EINVAL; ++ } ++ ++ array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); ++ bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); ++ if (!bank) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bank); ++ ++ for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { ++ field.reg = base + i * stride; ++ field.lsb = 0; ++ field.msb = 32; ++ ++ bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, ++ regmap, field); ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = hwspin_lock_register(bank, &pdev->dev, &qcom_hwspinlock_ops, ++ 0, QCOM_MUTEX_NUM_LOCKS); ++ if (ret) ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int qcom_hwspinlock_remove(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = hwspin_lock_unregister(bank); ++ if (ret) { ++ dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_hwspinlock_driver = { ++ .probe = qcom_hwspinlock_probe, ++ .remove = qcom_hwspinlock_remove, ++ .driver = { ++ .name = "qcom_hwspinlock", ++ .of_match_table = qcom_hwspinlock_of_match, ++ }, ++}; ++ ++static int __init qcom_hwspinlock_init(void) ++{ ++ return platform_driver_register(&qcom_hwspinlock_driver); ++} ++/* board init code might need to reserve hwspinlocks for predefined purposes */ ++postcore_initcall(qcom_hwspinlock_init); ++ ++static void __exit qcom_hwspinlock_exit(void) ++{ ++ platform_driver_unregister(&qcom_hwspinlock_driver); ++} ++module_exit(qcom_hwspinlock_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs"); diff --git a/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch b/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch new file mode 100644 index 0000000..70d5a58 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch @@ -0,0 +1,26 @@ +From bd5717a4632cdecafe82d03de7dcb3b1876e2828 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Fri, 26 Jun 2015 14:47:21 -0700 +Subject: [PATCH] hwspinlock: qcom: Correct msb in regmap_field + +msb of the regmap_field was mistakenly given the value 32, to set all bits +in the regmap update mask; although incorrect this worked until 921cc294, +where the mask calculation was corrected. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/qcom_hwspinlock.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -123,7 +123,7 @@ static int qcom_hwspinlock_probe(struct + for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { + field.reg = base + i * stride; + field.lsb = 0; +- field.msb = 32; ++ field.msb = 31; + + bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, + regmap, field); diff --git a/target/linux/ipq806x/patches-3.18/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-3.18/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch new file mode 100644 index 0000000..0d53a73 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch @@ -0,0 +1,20 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -291,5 +291,17 @@ + #clock-cells = <1>; + #reset-cells = <1>; + }; ++ ++ sfpb_mutex_block: syscon@01200600 { ++ compatible = "syscon"; ++ reg = <0x01200600 0x100>; ++ }; ++ ++ sfpb_mutex: sfpb-mutex { ++ compatible = "qcom,sfpb-mutex"; ++ syscon = <&sfpb_mutex_block 4 4>; ++ ++ #hwlock-cells = <1>; ++ }; + }; + }; diff --git a/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch b/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch index 5fee6ad..d430572 100644 --- a/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch +++ b/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch @@ -32,9 +32,9 @@ }; --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -291,5 +291,90 @@ - #clock-cells = <1>; - #reset-cells = <1>; +@@ -303,5 +303,90 @@ + + #hwlock-cells = <1>; }; + + hs_phy_1: phy@100f8800 { diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch index ed66047..66f305e 100644 --- a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch +++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch @@ -134,8 +134,8 @@ Signed-off-by: Mathieu Olivari / { model = "Qualcomm IPQ8064"; -@@ -306,6 +308,129 @@ - #reset-cells = <1>; +@@ -318,6 +320,129 @@ + #hwlock-cells = <1>; }; + pcie0: pci@1b500000 { diff --git a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch index 13ff921..99bd360 100644 --- a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch +++ b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -336,15 +336,21 @@ +@@ -348,15 +348,21 @@ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, @@ -26,7 +26,7 @@ status = "disabled"; }; -@@ -377,15 +383,21 @@ +@@ -389,15 +395,21 @@ clocks = <&gcc PCIE_1_A_CLK>, <&gcc PCIE_1_H_CLK>, @@ -52,7 +52,7 @@ status = "disabled"; }; -@@ -418,15 +430,21 @@ +@@ -430,15 +442,21 @@ clocks = <&gcc PCIE_2_A_CLK>, <&gcc PCIE_2_H_CLK>, diff --git a/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch b/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch index 4d9e613..8b137d7 100644 --- a/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch +++ b/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch @@ -13,7 +13,7 @@ Signed-off-by: Andy Gross --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -657,5 +657,25 @@ +@@ -669,5 +669,25 @@ }; }; diff --git a/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch b/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch index a2742b7..fe8e77c 100644 --- a/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch +++ b/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch @@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -677,5 +677,21 @@ +@@ -689,5 +689,21 @@ status = "disabled"; }; diff --git a/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch index 8cfc38b..7e7cd47 100644 --- a/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch +++ b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch @@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari }; --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -693,5 +693,91 @@ +@@ -705,5 +705,91 @@ status = "disabled"; }; diff --git a/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch b/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch new file mode 100644 index 0000000..04f35b7 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch @@ -0,0 +1,167 @@ +From fb7737e949e31d8a71acee6bbb670f32dbd2a2c0 Mon Sep 17 00:00:00 2001 +From: Suman Anna +Date: Wed, 4 Mar 2015 20:01:14 -0600 +Subject: [PATCH] hwspinlock/core: add device tree support + +This patch adds a new OF-friendly API of_hwspin_lock_get_id() +for hwspinlock clients to use/request locks from a hwspinlock +device instantiated through a device-tree blob. This new API +can be used by hwspinlock clients to get the id for a specific +lock using the phandle + args specifier, so that it can be +requested using the available hwspin_lock_request_specific() +API. + +Signed-off-by: Suman Anna +Reviewed-by: Bjorn Andersson +[small comment clarification] +Signed-off-by: Ohad Ben-Cohen +--- + Documentation/hwspinlock.txt | 10 +++++ + drivers/hwspinlock/hwspinlock_core.c | 79 ++++++++++++++++++++++++++++++++++++ + include/linux/hwspinlock.h | 7 ++++ + 3 files changed, 96 insertions(+) + +--- a/Documentation/hwspinlock.txt ++++ b/Documentation/hwspinlock.txt +@@ -48,6 +48,16 @@ independent, drivers. + ids for predefined purposes. + Should be called from a process context (might sleep). + ++ int of_hwspin_lock_get_id(struct device_node *np, int index); ++ - retrieve the global lock id for an OF phandle-based specific lock. ++ This function provides a means for DT users of a hwspinlock module ++ to get the global lock id of a specific hwspinlock, so that it can ++ be requested using the normal hwspin_lock_request_specific() API. ++ The function returns a lock id number on success, -EPROBE_DEFER if ++ the hwspinlock device is not yet registered with the core, or other ++ error values. ++ Should be called from a process context (might sleep). ++ + int hwspin_lock_free(struct hwspinlock *hwlock); + - free a previously-assigned hwspinlock; returns 0 on success, or an + appropriate error code on failure (e.g. -EINVAL if the hwspinlock +--- a/drivers/hwspinlock/hwspinlock_core.c ++++ b/drivers/hwspinlock/hwspinlock_core.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "hwspinlock_internal.h" + +@@ -257,6 +258,84 @@ void __hwspin_unlock(struct hwspinlock * + } + EXPORT_SYMBOL_GPL(__hwspin_unlock); + ++/** ++ * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id ++ * @bank: the hwspinlock device bank ++ * @hwlock_spec: hwlock specifier as found in the device tree ++ * ++ * This is a simple translation function, suitable for hwspinlock platform ++ * drivers that only has a lock specifier length of 1. ++ * ++ * Returns a relative index of the lock within a specified bank on success, ++ * or -EINVAL on invalid specifier cell count. ++ */ ++static inline int ++of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) ++{ ++ if (WARN_ON(hwlock_spec->args_count != 1)) ++ return -EINVAL; ++ ++ return hwlock_spec->args[0]; ++} ++ ++/** ++ * of_hwspin_lock_get_id() - get lock id for an OF phandle-based specific lock ++ * @np: device node from which to request the specific hwlock ++ * @index: index of the hwlock in the list of values ++ * ++ * This function provides a means for DT users of the hwspinlock module to ++ * get the global lock id of a specific hwspinlock using the phandle of the ++ * hwspinlock device, so that it can be requested using the normal ++ * hwspin_lock_request_specific() API. ++ * ++ * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock ++ * device is not yet registered, -EINVAL on invalid args specifier value or an ++ * appropriate error as returned from the OF parsing of the DT client node. ++ */ ++int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ struct of_phandle_args args; ++ struct hwspinlock *hwlock; ++ struct radix_tree_iter iter; ++ void **slot; ++ int id; ++ int ret; ++ ++ ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, ++ &args); ++ if (ret) ++ return ret; ++ ++ /* Find the hwspinlock device: we need its base_id */ ++ ret = -EPROBE_DEFER; ++ rcu_read_lock(); ++ radix_tree_for_each_slot(slot, &hwspinlock_tree, &iter, 0) { ++ hwlock = radix_tree_deref_slot(slot); ++ if (unlikely(!hwlock)) ++ continue; ++ ++ if (hwlock->bank->dev->of_node == args.np) { ++ ret = 0; ++ break; ++ } ++ } ++ rcu_read_unlock(); ++ if (ret < 0) ++ goto out; ++ ++ id = of_hwspin_lock_simple_xlate(&args); ++ if (id < 0 || id >= hwlock->bank->num_locks) { ++ ret = -EINVAL; ++ goto out; ++ } ++ id += hwlock->bank->base_id; ++ ++out: ++ of_node_put(args.np); ++ return ret ? ret : id; ++} ++EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id); ++ + static int hwspin_lock_register_single(struct hwspinlock *hwlock, int id) + { + struct hwspinlock *tmp; +--- a/include/linux/hwspinlock.h ++++ b/include/linux/hwspinlock.h +@@ -26,6 +26,7 @@ + #define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ + + struct device; ++struct device_node; + struct hwspinlock; + struct hwspinlock_device; + struct hwspinlock_ops; +@@ -66,6 +67,7 @@ int hwspin_lock_unregister(struct hwspin + struct hwspinlock *hwspin_lock_request(void); + struct hwspinlock *hwspin_lock_request_specific(unsigned int id); + int hwspin_lock_free(struct hwspinlock *hwlock); ++int of_hwspin_lock_get_id(struct device_node *np, int index); + int hwspin_lock_get_id(struct hwspinlock *hwlock); + int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, + unsigned long *); +@@ -120,6 +122,11 @@ void __hwspin_unlock(struct hwspinlock * + { + } + ++static inline int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ return 0; ++} ++ + static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) + { + return 0; diff --git a/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch b/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch new file mode 100644 index 0000000..581b199 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch @@ -0,0 +1,234 @@ +From 19a0f61224d2d91860fa8291ab63cb104ee86bdd Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Tue, 24 Mar 2015 10:11:05 -0700 +Subject: [PATCH] hwspinlock: qcom: Add support for Qualcomm HW Mutex block + +Add driver for Qualcomm Hardware Mutex block found in many Qualcomm +SoCs. + +Based on initial effort by Kumar Gala + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Reviewed-by: Jeffrey Hugo +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/Kconfig | 12 +++ + drivers/hwspinlock/Makefile | 1 + + drivers/hwspinlock/qcom_hwspinlock.c | 181 +++++++++++++++++++++++++++++++++++ + 3 files changed, 194 insertions(+) + create mode 100644 drivers/hwspinlock/qcom_hwspinlock.c + +--- a/drivers/hwspinlock/Kconfig ++++ b/drivers/hwspinlock/Kconfig +@@ -18,6 +18,18 @@ config HWSPINLOCK_OMAP + + If unsure, say N. + ++config HWSPINLOCK_QCOM ++ tristate "Qualcomm Hardware Spinlock device" ++ depends on ARCH_QCOM ++ select HWSPINLOCK ++ select MFD_SYSCON ++ help ++ Say y here to support the Qualcomm Hardware Mutex functionality, which ++ provides a synchronisation mechanism for the various processors on ++ the SoC. ++ ++ If unsure, say N. ++ + config HSEM_U8500 + tristate "STE Hardware Semaphore functionality" + depends on ARCH_U8500 +--- a/drivers/hwspinlock/Makefile ++++ b/drivers/hwspinlock/Makefile +@@ -4,4 +4,5 @@ + + obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o + obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o ++obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o + obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +--- /dev/null ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2015, Sony Mobile Communications AB ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++#define QCOM_MUTEX_APPS_PROC_ID 1 ++#define QCOM_MUTEX_NUM_LOCKS 32 ++ ++static int qcom_hwspinlock_trylock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) ++ return ret; ++ ++ return lock_owner == QCOM_MUTEX_APPS_PROC_ID; ++} ++ ++static void qcom_hwspinlock_unlock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) { ++ pr_err("%s: unable to query spinlock owner\n", __func__); ++ return; ++ } ++ ++ if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) { ++ pr_err("%s: spinlock not owned by us (actual owner is %d)\n", ++ __func__, lock_owner); ++ } ++ ++ ret = regmap_field_write(field, 0); ++ if (ret) ++ pr_err("%s: failed to unlock spinlock\n", __func__); ++} ++ ++static const struct hwspinlock_ops qcom_hwspinlock_ops = { ++ .trylock = qcom_hwspinlock_trylock, ++ .unlock = qcom_hwspinlock_unlock, ++}; ++ ++static const struct of_device_id qcom_hwspinlock_of_match[] = { ++ { .compatible = "qcom,sfpb-mutex" }, ++ { .compatible = "qcom,tcsr-mutex" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); ++ ++static int qcom_hwspinlock_probe(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank; ++ struct device_node *syscon; ++ struct reg_field field; ++ struct regmap *regmap; ++ size_t array_size; ++ u32 stride; ++ u32 base; ++ int ret; ++ int i; ++ ++ syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); ++ if (!syscon) { ++ dev_err(&pdev->dev, "no syscon property\n"); ++ return -ENODEV; ++ } ++ ++ regmap = syscon_node_to_regmap(syscon); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no offset in syscon\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no stride syscon\n"); ++ return -EINVAL; ++ } ++ ++ array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); ++ bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); ++ if (!bank) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bank); ++ ++ for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { ++ field.reg = base + i * stride; ++ field.lsb = 0; ++ field.msb = 32; ++ ++ bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, ++ regmap, field); ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = hwspin_lock_register(bank, &pdev->dev, &qcom_hwspinlock_ops, ++ 0, QCOM_MUTEX_NUM_LOCKS); ++ if (ret) ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int qcom_hwspinlock_remove(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = hwspin_lock_unregister(bank); ++ if (ret) { ++ dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_hwspinlock_driver = { ++ .probe = qcom_hwspinlock_probe, ++ .remove = qcom_hwspinlock_remove, ++ .driver = { ++ .name = "qcom_hwspinlock", ++ .of_match_table = qcom_hwspinlock_of_match, ++ }, ++}; ++ ++static int __init qcom_hwspinlock_init(void) ++{ ++ return platform_driver_register(&qcom_hwspinlock_driver); ++} ++/* board init code might need to reserve hwspinlocks for predefined purposes */ ++postcore_initcall(qcom_hwspinlock_init); ++ ++static void __exit qcom_hwspinlock_exit(void) ++{ ++ platform_driver_unregister(&qcom_hwspinlock_driver); ++} ++module_exit(qcom_hwspinlock_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs"); diff --git a/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch b/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch new file mode 100644 index 0000000..70d5a58 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch @@ -0,0 +1,26 @@ +From bd5717a4632cdecafe82d03de7dcb3b1876e2828 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Fri, 26 Jun 2015 14:47:21 -0700 +Subject: [PATCH] hwspinlock: qcom: Correct msb in regmap_field + +msb of the regmap_field was mistakenly given the value 32, to set all bits +in the regmap update mask; although incorrect this worked until 921cc294, +where the mask calculation was corrected. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/qcom_hwspinlock.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -123,7 +123,7 @@ static int qcom_hwspinlock_probe(struct + for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { + field.reg = base + i * stride; + field.lsb = 0; +- field.msb = 32; ++ field.msb = 31; + + bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, + regmap, field); diff --git a/target/linux/ipq806x/patches-4.1/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-4.1/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch new file mode 100644 index 0000000..027ff08 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch @@ -0,0 +1,21 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -67,6 +67,18 @@ + clock-frequency = <32768>; + #clock-cells = <0>; + }; ++ ++ sfpb_mutex_block: syscon@01200600 { ++ compatible = "syscon"; ++ reg = <0x01200600 0x100>; ++ }; ++ ++ sfpb_mutex: sfpb-mutex { ++ compatible = "qcom,sfpb-mutex"; ++ syscon = <&sfpb_mutex_block 4 4>; ++ ++ #hwlock-cells = <1>; ++ }; + }; + + soc: soc { diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch index fc2fe0a..51a08fb 100644 --- a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch +++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch @@ -134,7 +134,7 @@ Signed-off-by: Mathieu Olivari / { model = "Qualcomm IPQ8064"; -@@ -329,5 +331,127 @@ +@@ -341,5 +343,127 @@ #reset-cells = <1>; }; diff --git a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch index 59b7fcc..40115a4 100644 --- a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch +++ b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -359,15 +359,21 @@ +@@ -371,15 +371,21 @@ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, @@ -26,7 +26,7 @@ status = "disabled"; }; -@@ -400,15 +406,21 @@ +@@ -412,15 +418,21 @@ clocks = <&gcc PCIE_1_A_CLK>, <&gcc PCIE_1_H_CLK>, @@ -52,7 +52,7 @@ status = "disabled"; }; -@@ -441,15 +453,21 @@ +@@ -453,15 +465,21 @@ clocks = <&gcc PCIE_2_A_CLK>, <&gcc PCIE_2_H_CLK>, diff --git a/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch b/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch index be80f4c..458dcd5 100644 --- a/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch +++ b/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch @@ -8,7 +8,7 @@ #include #include #include -@@ -92,6 +93,63 @@ +@@ -104,6 +105,63 @@ reg-names = "lpass-lpaif"; }; @@ -72,7 +72,7 @@ qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; reg = <0x800000 0x4000>; -@@ -136,6 +194,12 @@ +@@ -148,6 +206,12 @@ reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; diff --git a/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch b/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch index 9435de6..b25d955 100644 --- a/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch +++ b/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch @@ -37,7 +37,7 @@ }; }; -@@ -72,6 +90,46 @@ +@@ -84,6 +102,46 @@ }; }; @@ -84,7 +84,7 @@ soc: soc { #address-cells = <1>; #size-cells = <1>; -@@ -187,11 +245,13 @@ +@@ -199,11 +257,13 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; diff --git a/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch b/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch index bb9a194..e5c57a9 100644 --- a/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch +++ b/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch @@ -26,7 +26,7 @@ Signed-off-by: Andy Gross #address-cells = <1>; --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -595,5 +595,25 @@ +@@ -607,5 +607,25 @@ status = "disabled"; }; diff --git a/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch b/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch index 27eae8f..bd9bf47 100644 --- a/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch +++ b/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch @@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -615,5 +615,21 @@ +@@ -627,5 +627,21 @@ status = "disabled"; }; diff --git a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch index 4a43ae4..c21ebcd 100644 --- a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch +++ b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch @@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari }; --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -631,5 +631,91 @@ +@@ -643,5 +643,91 @@ status = "disabled"; };