From patchwork Fri Jun 5 07:42:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 481096 X-Patchwork-Delegate: jogo@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 73102140281 for ; Fri, 5 Jun 2015 17:44:00 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=MdVEZ59o; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id E136C28163A; Fri, 5 Jun 2015 09:42:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id E8CAB283F11 for ; Fri, 5 Jun 2015 09:41:54 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-wg0-f44.google.com (mail-wg0-f44.google.com [74.125.82.44]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Fri, 5 Jun 2015 09:41:54 +0200 (CEST) Received: by wgbgq6 with SMTP id gq6so50112176wgb.3 for ; Fri, 05 Jun 2015 00:43:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=AbXtlYAqh/pHHETAw14N9Idk76lsSXqxVi+zCtixODs=; b=MdVEZ59oLQDSc8po0OjK3US5rZqC8jhe3rWQe4CIRkLe4CofB0lasNfzieVUENbaGz /yQaWN8gXS/6XnXR4tA84GmJThSAmbuLBsYg/SilEZUOBNag4KXoxmfygB0WIDiVgzNT JhYJTlyD3d40w2RBwCA9m6ENmHR8ZEB7JTLiM0Vey+oJigPljvKRkJicMUNywyO+5lav /HAdkVoZXFpNgImAHdG5Q2bCyXBXIDHo5KpCWeeeOFQIIkpnVDwABMDbfwmsCgmiYmED TmNNjkz+CEIFvq8r+HqAbcf0sbax/cMRyQNvjktr1PwbqenaSEg33sqluAMgZZvZ98gh W0Jw== X-Received: by 10.180.74.144 with SMTP id t16mr15272096wiv.33.1433490209530; Fri, 05 Jun 2015 00:43:29 -0700 (PDT) Received: from orion.local ([5.2.198.78]) by mx.google.com with ESMTPSA id gj7sm2102077wib.4.2015.06.05.00.43.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Jun 2015 00:43:28 -0700 (PDT) From: Alexandru Ardelean To: openwrt-devel@lists.openwrt.org jogo@openwrt.org hauke@hauke-m.de Date: Fri, 5 Jun 2015 10:42:40 +0300 Message-Id: <1433490160-26464-1-git-send-email-ardeleanalex@gmail.com> X-Mailer: git-send-email 2.1.4 Subject: [OpenWrt-Devel] [PATCH] [RFC] b53: widen stp state mask to 3 bits (instead of 2) X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" At least on my b53 chip, the mask is 3 bits wide, and because of this some STP states are not set properly and discarded when read. Maybe for some other chips it makes sense to have just 2 bits width, but I don't have other versions around to test/validate. If that's the case then maybe we could add another STP state mask. Signed-off-by: Alexandru Ardelean --- target/linux/generic/files/drivers/net/phy/b53/b53_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h index eef5c81..144e1c8 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h @@ -65,7 +65,7 @@ #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ #define PORT_CTRL_STP_STATE_S 5 -#define PORT_CTRL_STP_STATE_MASK (0x3 << PORT_CTRL_STP_STATE_S) +#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) /* SMP Control Register (8 bit) */ #define B53_SMP_CTRL 0x0a