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[217.86.68.230]) by mx.google.com with ESMTPSA id r9sm24151391wjo.26.2015.05.11.12.08.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 May 2015 12:08:16 -0700 (PDT) From: Martin Blumenstingl To: openwrt-devel@lists.openwrt.org Date: Mon, 11 May 2015 21:07:39 +0200 Message-Id: <1431371259-5985-1-git-send-email-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.4.0 Subject: [OpenWrt-Devel] [PATCH] lantiq: Fix PCIe bus when PCI is also enabled. X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" The PCIe bus seems to require a hack/workaround when PCI is enabled as well. Unfortunately this is guarded by an CONFIG_IFX_PCI ifdef, which is only defined in lantiq's BSP code. The config symbol for the upstream lantiq PCI driver is CONFIG_PCI_LANTIQ. Signed-off-by: Martin Blumenstingl --- .../0001-MIPS-lantiq-add-pcie-driver.patch | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch index 2cc0814..26f262c 100644 --- a/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch +++ b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch @@ -4115,11 +4115,11 @@ Signed-off-by: John Crispin +{ + u32 tbus_number = bus_number; + -+#ifdef CONFIG_IFX_PCI ++#ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tbus_number -= pcibios_1st_host_bus_nr(); + } -+#endif /* CONFIG_IFX_PCI */ ++#endif /* CONFIG_PCI_LANTIQ */ + return tbus_number; +} + @@ -4141,14 +4141,14 @@ Signed-off-by: John Crispin + } + + if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCI ++ #ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); + } -+ #endif /* CONFIG_IFX_PCI */ ++ #endif /* CONFIG_PCI_LANTIQ */ + } + else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCI ++ #ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); + } @@ -5457,11 +5457,11 @@ Signed-off-by: John Crispin +{ + u32 tbus_number = bus_number; + -+#ifdef CONFIG_IFX_PCI ++#ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tbus_number -= pcibios_1st_host_bus_nr(); + } -+#endif /* CONFIG_IFX_PCI */ ++#endif /* CONFIG_PCI_LANTIQ */ + return tbus_number; +} + @@ -5483,14 +5483,14 @@ Signed-off-by: John Crispin + } + + if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCI ++ #ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); + } -+ #endif /* CONFIG_IFX_PCI */ ++ #endif /* CONFIG_PCI_LANTIQ */ + } + else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCI ++ #ifdef CONFIG_PCI_LANTIQ + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); + }