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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This reduces firmware size for SoCs which do not use this driver. Signed-off-by: Samuel Holland --- lib/utils/gpio/fdt_gpio_designware.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62b listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 T_SCC_BODY_TEXT_LINE No description available. X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This reduces firmware size for SoCs which do not use this driver. Signed-off-by: Samuel Holland --- lib/utils/gpio/fdt_gpio_designware.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/lib/utils/gpio/fdt_gpio_designware.c b/lib/utils/gpio/fdt_gpio_designware.c index 20701a15..fa2cd1f9 100644 --- a/lib/utils/gpio/fdt_gpio_designware.c +++ b/lib/utils/gpio/fdt_gpio_designware.c @@ -13,11 +13,11 @@ #include #include +#include #include #include -#define DW_GPIO_CHIP_MAX 4 /* need 1 per bank in use */ #define DW_GPIO_PINS_MAX 32 #define DW_GPIO_DDR 0x4 @@ -32,9 +32,6 @@ struct dw_gpio_chip { extern struct fdt_gpio fdt_gpio_designware; -static unsigned int dw_gpio_chip_count; -static struct dw_gpio_chip dw_gpio_chip_array[DW_GPIO_CHIP_MAX]; - #define pin_to_chip(__p) container_of((__p)->chip, struct dw_gpio_chip, chip); static int dw_gpio_direction_output(struct gpio_pin *gp, int value) @@ -86,9 +83,6 @@ static int dw_gpio_init_bank(const void *fdt, int nodeoff, u32 phandle, uint64_t addr; int rc, poff, nr_pins, bank, len; - if (dw_gpio_chip_count >= DW_GPIO_CHIP_MAX) - return SBI_ENOSPC; - /* need to get parent for the address property */ poff = fdt_parent_offset(fdt, nodeoff); if (poff < 0) @@ -110,7 +104,9 @@ static int dw_gpio_init_bank(const void *fdt, int nodeoff, u32 phandle, return SBI_EINVAL; nr_pins = fdt32_to_cpu(*val); - chip = &dw_gpio_chip_array[dw_gpio_chip_count]; + chip = sbi_zalloc(sizeof(*chip)); + if (!chip) + return SBI_ENOMEM; chip->dr = (void *)(uintptr_t)addr + (bank * 0xc); chip->ext = (void *)(uintptr_t)addr + (bank * 4) + 0x50; @@ -123,7 +119,6 @@ static int dw_gpio_init_bank(const void *fdt, int nodeoff, u32 phandle, if (rc) return rc; - dw_gpio_chip_count++; return 0; }