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([2a01:e0a:999:a3a0:a963:3072:e647:c890]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce73f5sm470275585e9.21.2024.05.21.06.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 06:58:43 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: opensbi@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Anup Patel , Atish Patra Subject: [PATCH v1 4/5] lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING Date: Tue, 21 May 2024 15:58:32 +0200 Message-ID: <20240521135835.371485-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240521135835.371485-1-cleger@rivosinc.com> References: <20240521135835.371485-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240521_145845_929925_13CAA32F X-CRM114-Status: GOOD ( 12.54 ) X-Spam-Score: 0.0 (/) X-Spam-Report: =?unknown-8bit?q?Spam_detection_software=2C_running_on_the_sy?= =?unknown-8bit?q?stem_=22desiato=2Einfradead=2Eorg=22=2C?= =?unknown-8bit?q?_has_NOT_identified_this_incoming_email_as_spam=2E__The_ori?= =?unknown-8bit?q?ginal?= =?unknown-8bit?q?_message_has_been_attached_to_this_so_you_can_view_it_or_la?= =?unknown-8bit?q?bel?= =?unknown-8bit?q?_similar_future_email=2E__If_you_have_any_questions=2C_see?= =?unknown-8bit?q?_the_administrator_of_that_system_for_details=2E?= =?unknown-8bit?q?_?= =?unknown-8bit?q?_Content_preview=3A__Add_support_for_SBI=5FFWFT=5FPTE=5FAD?= =?unknown-8bit?q?=5FHW=5FUPDATING_based_on_SVADU?= =?unknown-8bit?q?_presence=2E_Signed-off-by=3A_Cl=C3=A9ment_L=C3=A9ger_=3Ccl?= =?unknown-8bit?q?eger=40rivosinc=2Ecom=3E_---_lib/sbi/sbi=5Ffwft=2Ec?= =?unknown-8bit?q?_=7C_56_++++++++++++++++++++++++++++++++++++++++++++++_lib/?= =?unknown-8bit?q?sbi/sbi=5Fhsm=2Ec_=7C_12?= =?unknown-8bit?q?_++++++++++_2_files_changed=2C_68_insertions=28+=29_?= =?unknown-8bit?q?_?= =?unknown-8bit?q?_Content_analysis_details=3A___=280=2E0_points=2C_5=2E0_req?= =?unknown-8bit?q?uired=29?= =?unknown-8bit?q?_?= =?unknown-8bit?q?_pts_rule_name______________description?= =?unknown-8bit?q?_----_----------------------_------------------------------?= =?unknown-8bit?q?--------------------?= =?unknown-8bit?q?_-0=2E0_RCVD=5FIN=5FDNSWL=5FNONE_____RBL=3A_Sender_listed_a?= =?unknown-8bit?q?t_https=3A//www=2Ednswl=2Eorg/=2C_no?= =?unknown-8bit?q?_trust?= =?unknown-8bit?b?IFsyYTAwOjE0NTA6NDg2NDoyMDowOjA6MDo0MzAgbGlzdGVkIGluXQ==?= =?unknown-8bit?b?IFtsaXN0LmRuc3dsLm9yZ10=?= =?unknown-8bit?q?_0=2E0_SPF=5FHELO=5FNONE__________SPF=3A_HELO_does_not_publ?= =?unknown-8bit?q?ish_an_SPF_Record?= =?unknown-8bit?q?_-0=2E0_SPF=5FPASS_______________SPF=3A_sender_matches_SPF_?= =?unknown-8bit?q?record?= =?unknown-8bit?q?_-0=2E1_DKIM=5FVALID_____________Message_has_at_least_one_v?= =?unknown-8bit?q?alid_DKIM_or_DK_signature?= =?unknown-8bit?q?_0=2E1_DKIM=5FSIGNED____________Message_has_a_DKIM_or_DK_si?= =?unknown-8bit?q?gnature=2C_not_necessarily_valid?= X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add support for SBI_FWFT_PTE_AD_HW_UPDATING based on SVADU presence. Signed-off-by: Clément Léger --- lib/sbi/sbi_fwft.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ lib/sbi/sbi_hsm.c | 12 ++++++++++ 2 files changed, 68 insertions(+) diff --git a/lib/sbi/sbi_fwft.c b/lib/sbi/sbi_fwft.c index 54c6642..bf5d4d4 100644 --- a/lib/sbi/sbi_fwft.c +++ b/lib/sbi/sbi_fwft.c @@ -101,6 +101,56 @@ static int fwft_get_misaligned_delegation(struct fwft_config *conf, return SBI_OK; } +static int fwft_adue_supported(struct fwft_config *conf) +{ + if (!sbi_hart_has_extension(sbi_scratch_thishart_ptr(), + SBI_HART_EXT_SVADU)) + return SBI_ENOTSUPP; + + return SBI_OK; +} + +#if __riscv_xlen == 32 +#define MENVCFG_REG(__val) \ + (__builtin_ffsll(__val) > 32 ? CSR_MENVCFGH : CSR_MENVCFG) +#define MENVCFG_VAL(__val) \ + (__builtin_ffsll(__val) > 32 ? (__val) >> 32 : (__val)) +#else +#define MENVCFG_REG(__val) CSR_MENVCFG +#define MENVCFG_VAL(__val) (__val) +#endif + +static int fwft_set_adue(struct fwft_config *conf, unsigned long value) +{ + if (value) +#if __riscv_xlen == 32 + csr_set(CSR_MENVCFGH, ENVCFG_ADUE >> 32); +#else + csr_set(CSR_MENVCFG, ENVCFG_ADUE); +#endif + else +#if __riscv_xlen == 32 + csr_clear(CSR_MENVCFGH, ENVCFG_ADUE >> 32); +#else + csr_clear(CSR_MENVCFG, ENVCFG_ADUE); +#endif + + return SBI_OK; +} + +static int fwft_get_adue(struct fwft_config *conf, unsigned long *value) +{ + unsigned long cfg; +#if __riscv_xlen == 32 + cfg = csr_read(CSR_MENVCFGH) & (ENVCFG_ADUE >> 32); +#else + cfg = csr_read(CSR_MENVCFG) & ENVCFG_ADUE; +#endif + *value = cfg != 0; + + return SBI_OK; +} + static struct fwft_config* get_feature_config(enum sbi_fwft_feature_t feature) { int i; @@ -186,6 +236,12 @@ static const struct fwft_feature features[] = .set = fwft_set_misaligned_delegation, .get = fwft_get_misaligned_delegation, }, + { + .id = SBI_FWFT_PTE_AD_HW_UPDATING, + .supported = fwft_adue_supported, + .set = fwft_set_adue, + .get = fwft_get_adue, + }, }; int sbi_fwft_init(struct sbi_scratch *scratch, bool cold_boot) diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c index 47edab2..9a74d2c 100644 --- a/lib/sbi/sbi_hsm.c +++ b/lib/sbi/sbi_hsm.c @@ -45,6 +45,10 @@ struct sbi_hsm_data { unsigned long saved_mie; unsigned long saved_mip; unsigned long saved_hedeleg; + unsigned long saved_menvcfg; +#if __riscv_xlen == 32 + unsigned long saved_menvcfgh; +#endif atomic_t start_ticket; }; @@ -419,6 +423,10 @@ void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch) hdata->saved_mie = csr_read(CSR_MIE); hdata->saved_mip = csr_read(CSR_MIP) & (MIP_SSIP | MIP_STIP); hdata->saved_hedeleg = csr_read(CSR_HEDELEG); +#if __riscv_xlen == 32 + hdata->saved_menvcfgh = csr_read(CSR_MENVCFGH); +#endif + hdata->saved_menvcfg = csr_read(CSR_MENVCFG); } static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch) @@ -426,6 +434,10 @@ static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch) struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset); + csr_write(CSR_MENVCFG, hdata->saved_menvcfg); +#if __riscv_xlen == 32 + csr_write(CSR_MENVCFGH, hdata->saved_menvcfgh); +#endif csr_write(CSR_HEDELEG, hdata->saved_hedeleg); csr_write(CSR_MIE, hdata->saved_mie); csr_set(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP)));