From patchwork Thu Nov 30 12:42:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1870108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=3m7+xyQV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SgwpX4f9Pz23nw for ; Thu, 30 Nov 2023 23:43:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZW+b2p2rXoHpI5MYb8kVUuk9ZniWQBv6yHlFubXAGak=; b=3m7+xyQVWz5OI/ 4VrpNeqsO4QD4Lgt3XcSYBgllBAitH7YtLQvK+qqqz/k/VaKtEAtnxVtCqJysVD3Xw5xoiGr7CDmQ bF+02D0PKy7qY6uF9NhnuXEnEMGAo++wOWdVQvB/x8ClpZ5BO3KXf+WwFGbyCk/Obj/oifNUQKQqt sbOIYBvhUJkl0rEZsBH4/NNkOaNtNI1XfaNpqkkjt/2/KMiusQOIyXEkgeBVVqjc5XBhBd5VDCgJf 3FIoiV48hOJhsKXUbnaMQJeA46QW8cNkGxoWViAWD9rwZfjHdH26SWWjC3RophSEMowbtmfDTTXth mPj2donadzF4Afh8tdpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8gNl-00AtIq-1K; Thu, 30 Nov 2023 12:43:05 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8gNi-00AtHT-0f for opensbi@lists.infradead.org; Thu, 30 Nov 2023 12:43:03 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AUCgiQp055975; Thu, 30 Nov 2023 20:42:44 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 30 Nov 2023 20:42:39 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , , Yu Chien Peter Lin Subject: [PATCH v4 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Date: Thu, 30 Nov 2023 20:42:02 +0800 Message-ID: <20231130124213.2590640-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130124213.2590640-1-peterlin@andestech.com> References: <20231130124213.2590640-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3AUCgiQp055975 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_044302_691627_267FD5C5 X-CRM114-Status: GOOD ( 13.61 ) X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add support for custom PMU extensions to set inhibit bits on custom CSRs by introducing the PMU device callback hw_counter_filter_mode(). This allows the perf tool to restrict event counting under a s [...] Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add support for custom PMU extensions to set inhibit bits on custom CSRs by introducing the PMU device callback hw_counter_filter_mode(). This allows the perf tool to restrict event counting under a specified privileged mode by appending a modifier, e.g. perf record -e event:k to count events only happening in kernel mode. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Anup Patel --- Changes v1 -> v2: - No change Changes v2 -> v3: - Add pmu_dev->hw_counter_filter_mode() in pmu_fixed_ctr_update_inhibit_bits() Changes v3 -> v4: - Check pmu_dev->hw_counter_filter_mode() instead of custom extension in pmu_fixed_ctr_update_inhibit_bits() --- include/sbi/sbi_pmu.h | 6 ++++++ lib/sbi/sbi_pmu.c | 20 ++++++++++++++------ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 16f6877..d63149c 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -89,6 +89,12 @@ struct sbi_pmu_device { * Custom function returning the machine-specific irq-bit. */ int (*hw_counter_irq_bit)(void); + + /** + * Custom function to inhibit counting of events while in + * specified mode. + */ + void (*hw_counter_filter_mode)(unsigned long flags, int counter_index); }; /** Get the PMU platform device */ diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 2ee6e62..4b0f5be 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, pmu_dev->hw_counter_disable_irq(ctr_idx); /* Update the inhibit flags based on inhibit flags received from supervisor */ - pmu_update_inhibit_flags(flags, &mhpmevent_val); + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF)) + pmu_update_inhibit_flags(flags, &mhpmevent_val); + if (pmu_dev && pmu_dev->hw_counter_filter_mode) + pmu_dev->hw_counter_filter_mode(flags, ctr_idx); #if __riscv_xlen == 32 csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF); @@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags) #if __riscv_xlen == 32 uint64_t cfgh_csr_no; #endif - if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) + if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) && + !(pmu_dev && pmu_dev->hw_counter_filter_mode)) return fixed_ctr; switch (fixed_ctr) { @@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags) } cfg_val |= MHPMEVENT_MINH; - pmu_update_inhibit_flags(flags, &cfg_val); + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) { + pmu_update_inhibit_flags(flags, &cfg_val); #if __riscv_xlen == 32 - csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF); - csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG); + csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF); + csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG); #else - csr_write_num(cfg_csr_no, cfg_val); + csr_write_num(cfg_csr_no, cfg_val); #endif + } + if (pmu_dev && pmu_dev->hw_counter_filter_mode) + pmu_dev->hw_counter_filter_mode(flags, fixed_ctr); return fixed_ctr; }