From patchwork Wed Nov 22 07:36:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1867199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=K4gqfQvj; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SZtVR3WDfz1ySN for ; Wed, 22 Nov 2023 18:41:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MhfV/Q8s7X8ol1ILjsPRBIdZRDQPSOlesyyF2G3jX8A=; b=K4gqfQvjZG9CXV Sim6cf/9rZHCEBdUHOJ4hNyRIoHs4Kezxxpe2T1dsqk7ff1B+QFCOSOL+RXjg7YQHNTgs1Ktx8cUk Wu6Uvnq/NBXKz4R3fTdWtfkBKjEoqPRswPkvPT/TFcV0Cqi96VHb4aRLNnWBX1k75xiR2yr6qQqY/ bQBxsnaIDwDKSwPAY+zXxuM6pVscoc5YpYsmKQpRHV+NDwPlI096lzJSXDSKsOD4NzqreOmRg5vO0 L/nh6O3rUxynSG5c3yHlmBO+q9CLNCZ0Dbk5DHF+4iARhBH2ObvxhgCNu+S1gIqoTA0whFOsZng7W VlYCvwqkaxHpUiadx75w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r5hrf-000wQB-1s; Wed, 22 Nov 2023 07:41:39 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5hrZ-000wMh-15 for opensbi@lists.infradead.org; Wed, 22 Nov 2023 07:41:37 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AM7et11091305; Wed, 22 Nov 2023 15:40:55 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 22 Nov 2023 15:40:51 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH v3 15/15] docs: pmu: Add Andes PMU node example Date: Wed, 22 Nov 2023 15:36:17 +0800 Message-ID: <20231122073617.379441-16-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122073617.379441-1-peterlin@andestech.com> References: <20231122073617.379441-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3AM7et11091305 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231121_234133_818054_8382E776 X-CRM114-Status: UNSURE ( 7.75 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.5 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add PMU node example for event index to counter index mapping and selector value translation of Andes' CPUs. Currently, there are 4 HPM counters that can be used to monitor all of the events for each hart. Content analysis details: (0.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 URIBL_CSS Contains an URL's NS IP listed in the Spamhaus CSS blocklist [URIs: exec.it] 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add PMU node example for event index to counter index mapping and selector value translation of Andes' CPUs. Currently, there are 4 HPM counters that can be used to monitor all of the events for each hart. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Locus Wei-Han Chen Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel Reviewed-by: Lad Prabhakar --- Changes v1 -> v2: - sync up with datasheet Changes v2 -> v3: - Include Anup's RB tag --- docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/docs/pmu_support.md b/docs/pmu_support.md index 8cfa08c..9b48f1e 100644 --- a/docs/pmu_support.md +++ b/docs/pmu_support.md @@ -125,3 +125,85 @@ pmu { <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; }; ``` + +### Example 3 + +``` +/* + * For Andes 45-series platforms. The encodings can be found in the + * "Machine Performance Monitoring Event Selector" section + * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + */ +pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */ + <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */ + <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */ + <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */ + <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */ + <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */ + <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */ + <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */ + <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */ + <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */ + <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */ + <0x10009 0x0000 0x31>; /* L1I_READ_MISS -> I-Cache miss */ + riscv,event-to-mhpmcounters = <0x1 0x6 0x78>, + <0x10000 0x10003 0x78>, + <0x10008 0x10009 0x78>; + riscv,raw-event-to-mhpmcounters = + <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */ + <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */ + <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */ + <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */ + <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */ + <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */ + <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */ + <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */ + <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */ + <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */ + <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */ + <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */ + <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */ + <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */ + <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */ + <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */ + <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */ + <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */ + <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */ + <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */ + <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */ + <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */ + <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */ + <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */ + <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */ + <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */ + <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */ + <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */ + <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */ + <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */ + <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */ + <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */ + <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */ + <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */ + <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */ + <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */ + <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */ + <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */ + <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */ + <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */ + <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */ + <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */ + <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */ + <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */ + <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */ + <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */ + <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */ + <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */ + <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */ + <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */ + <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */ + <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */ +}; +```