diff mbox series

[v2,03/11] platform: include: andes45: Add PMU related CSR defines

Message ID 20231019113713.3508153-4-peterlin@andestech.com
State Changes Requested
Headers show
Series Add Andes PMU extension support | expand

Commit Message

Yu-Chien Peter Lin Oct. 19, 2023, 11:37 a.m. UTC 
This patch adds CSR for Andes PMU extension.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
  - Rename andes_pmu() -> has_andes_pmu()
---
 platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Anup Patel Nov. 16, 2023, 6:39 a.m. UTC | #1 
On Thu, Oct 19, 2023 at 5:10 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch adds CSR for Andes PMU extension.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
> Changes v1 -> v2:
>   - Rename andes_pmu() -> has_andes_pmu()
> ---
>  platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index f570994..ce31617 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -12,6 +12,17 @@
>  #define CSR_MDCM_CFG           0xfc1
>  #define CSR_MMSC_CFG           0xfc2
>
> +/* Machine Trap Related Registers */
> +#define CSR_MSLIDELEG          0x7d5
> +
> +/* Counter Related Registers */
> +#define CSR_MCOUNTERWEN                0x7ce
> +#define CSR_MCOUNTERINTEN      0x7cf
> +#define CSR_MCOUNTERMASK_M     0x7d1
> +#define CSR_MCOUNTERMASK_S     0x7d2
> +#define CSR_MCOUNTERMASK_U     0x7d3
> +#define CSR_MCOUNTEROVF                0x7d4
> +
>  #define MICM_CFG_ISZ_OFFSET            6
>  #define MICM_CFG_ISZ_MASK              (0x7  << MICM_CFG_ISZ_OFFSET)
>
> @@ -26,4 +37,19 @@
>  #define MCACHE_CTL_CCTL_SUEN_OFFSET    8
>  #define MCACHE_CTL_CCTL_SUEN_MASK      (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
>
> +/* Performance monitor */
> +#define MMSC_CFG_PMNDS_MASK            (1 << 15)
> +#define MIP_PMOVI                      (1 << 18)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define has_andes_pmu()                                        \
> +({                                                     \
> +       (((csr_read(CSR_MMSC_CFG) &                     \
> +          MMSC_CFG_PMNDS_MASK)                         \
> +         && misa_extension('S')) ? true : false);      \
> +})
> +
> +#endif /* __ASSEMBLER__ */
> +
>  #endif /* _RISCV_ANDES45_H */
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index f570994..ce31617 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -12,6 +12,17 @@ 
 #define CSR_MDCM_CFG		0xfc1
 #define CSR_MMSC_CFG		0xfc2
 
+/* Machine Trap Related Registers */
+#define CSR_MSLIDELEG		0x7d5
+
+/* Counter Related Registers */
+#define CSR_MCOUNTERWEN		0x7ce
+#define CSR_MCOUNTERINTEN	0x7cf
+#define CSR_MCOUNTERMASK_M	0x7d1
+#define CSR_MCOUNTERMASK_S	0x7d2
+#define CSR_MCOUNTERMASK_U	0x7d3
+#define CSR_MCOUNTEROVF		0x7d4
+
 #define MICM_CFG_ISZ_OFFSET		6
 #define MICM_CFG_ISZ_MASK		(0x7  << MICM_CFG_ISZ_OFFSET)
 
@@ -26,4 +37,19 @@ 
 #define MCACHE_CTL_CCTL_SUEN_OFFSET	8
 #define MCACHE_CTL_CCTL_SUEN_MASK	(0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
 
+/* Performance monitor */
+#define MMSC_CFG_PMNDS_MASK		(1 << 15)
+#define MIP_PMOVI			(1 << 18)
+
+#ifndef __ASSEMBLER__
+
+#define has_andes_pmu()					\
+({							\
+	(((csr_read(CSR_MMSC_CFG) &			\
+	   MMSC_CFG_PMNDS_MASK)				\
+	  && misa_extension('S')) ? true : false);	\
+})
+
+#endif /* __ASSEMBLER__ */
+
 #endif /* _RISCV_ANDES45_H */