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[v3,01/10] include: sbi: Add macro definitions for mseccfg CSR

Message ID 20230712043436.100548-2-hchauhan@ventanamicro.com
State Accepted
Headers show
Series Add support for Smepmp | expand

Commit Message

Himanshu Chauhan July 12, 2023, 4:34 a.m. UTC 
- Add macros for Machine Security Configuration (mseccfg) CSR
- Add macros to access/manipulate bits in msecfg CSR

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 include/sbi/riscv_encoding.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 4ebed97..50071ad 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -663,6 +663,18 @@ 
 #define CSR_MHPMEVENT30H		0x73e
 #define CSR_MHPMEVENT31H		0x73f
 
+/* Machine Security Configuration CSR (mseccfg) */
+#define CSR_MSECCFG_LOWER		0x747
+#define CSR_MSECCFG_UPPER		0x757
+#define CSR_MSECCFG			(CSR_MSECCFG_LOWER)
+
+#define MSECCFG_MML_SHIFT		(0)
+#define MSECCFG_MML			(_UL(1) << MSECCFG_MML_SHIFT)
+#define MSECCFG_MMWP_SHIFT		(1)
+#define MSECCFG_MMWP			(_UL(1) << MSECCFG_MMWP_SHIFT)
+#define MSECCFG_RLB_SHIFT		(2)
+#define MSECCFG_RLB			(_UL(1) << MSECCFG_RLB_SHIFT)
+
 /* Counter Overflow CSR */
 #define CSR_SCOUNTOVF			0xda0