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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Smepmp specification defines a truth table based on which the access is allowed to different modes. This patch adds different flags based on this truth table. Signed-off-by: Himanshu Chauhan --- include/sbi/sbi_domain.h | 51 +++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 6 deletions(-) Content analysis details: (0.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:533 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Smepmp specification defines a truth table based on which the access is allowed to different modes. This patch adds different flags based on this truth table. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/sbi_domain.h | 51 +++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h index b05bcf4..24d3dc1 100644 --- a/include/sbi/sbi_domain.h +++ b/include/sbi/sbi_domain.h @@ -43,6 +43,51 @@ struct sbi_domain_memregion { #define SBI_DOMAIN_MEMREGION_SU_WRITABLE (1UL << 4) #define SBI_DOMAIN_MEMREGION_SU_EXECUTABLE (1UL << 5) +#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0x3fUL) +#define SBI_DOMAIN_MEMREGION_M_ACCESS_MASK (0x7UL) +#define SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK (0x38UL) + +#define SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT (3) + +#define SBI_DOMAIN_MEMREGION_SHARED_RDONLY \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUX_MRX \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_EXECUTABLE | \ + SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUX_MX \ + (SBI_DOMAIN_MEMREGION_M_EXECUTABLE | \ + SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_WRITABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE| \ + SBI_DOMAIN_MEMREGION_SU_WRITABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUR_MRW \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_WRITABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE) + +#define SBI_DOMAIN_MEMREGION_IS_SHARED(_flags) \ + ((_flags == SBI_DOMAIN_MEMREGION_SHARED_RDONLY) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUX_MRX) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUX_MX) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW)|| \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUR_MRW)) + +#define SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(__flags) \ + ((__flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK) && \ + !(__flags & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK)) + +#define SBI_DOMAIN_MEMREGION_SU_ONLY_ACCESS(__flags) \ + ((__flags & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK) && \ + !(__flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK)) + /** Bit to control if permissions are enforced on all modes */ #define SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS (1UL << 6) @@ -78,12 +123,6 @@ struct sbi_domain_memregion { (SBI_DOMAIN_MEMREGION_SU_EXECUTABLE | \ SBI_DOMAIN_MEMREGION_M_EXECUTABLE) -#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0x3fUL) -#define SBI_DOMAIN_MEMREGION_M_ACCESS_MASK (0x7UL) -#define SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK (0x38UL) - -#define SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT (3) - #define SBI_DOMAIN_MEMREGION_MMIO (1UL << 31) unsigned long flags; };