| Message ID | 20220315162240.40990-1-wxjstz@126.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [1/3] lib: pmp_set/pmp_get moved errors from runtime to compile time | expand |
On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz@126.com> wrote: > > pmp_set/pmp_get calculates the location of the CSR register separately > through conditional compilation. In the case of non-32-bit and 64-bit, > we can report an error directly through #error without putting it at > runtime > > Signed-off-by: Xiang W <wxjstz@126.com> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > lib/sbi/riscv_asm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c > index 847bdba..5eab1ed 100644 > --- a/lib/sbi/riscv_asm.c > +++ b/lib/sbi/riscv_asm.c > @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, > pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; > pmpcfg_shift = (n & 7) << 3; > #else > - return SBI_ENOTSUPP; > +# error "Unexpected __riscv_xlen" > #endif > pmpaddr_csr = CSR_PMPADDR0 + n; > > @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, > pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; > pmpcfg_shift = (n & 7) << 3; > #else > - return SBI_ENOTSUPP; > +# error "Unexpected __riscv_xlen" > #endif > pmpaddr_csr = CSR_PMPADDR0 + n; > > -- > 2.30.2 >
On Mon, Mar 21, 2022 at 6:15 PM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz@126.com> wrote: > > > > pmp_set/pmp_get calculates the location of the CSR register separately > > through conditional compilation. In the case of non-32-bit and 64-bit, > > we can report an error directly through #error without putting it at > > runtime > > > > Signed-off-by: Xiang W <wxjstz@126.com> > > Looks good to me. > > Reviewed-by: Anup Patel <anup@brainfault.org> Applied this patch to the riscv/opensbi repo. Thanks, Anup > > Regards, > Anup > > > --- > > lib/sbi/riscv_asm.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c > > index 847bdba..5eab1ed 100644 > > --- a/lib/sbi/riscv_asm.c > > +++ b/lib/sbi/riscv_asm.c > > @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, > > pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; > > pmpcfg_shift = (n & 7) << 3; > > #else > > - return SBI_ENOTSUPP; > > +# error "Unexpected __riscv_xlen" > > #endif > > pmpaddr_csr = CSR_PMPADDR0 + n; > > > > @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, > > pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; > > pmpcfg_shift = (n & 7) << 3; > > #else > > - return SBI_ENOTSUPP; > > +# error "Unexpected __riscv_xlen" > > #endif > > pmpaddr_csr = CSR_PMPADDR0 + n; > > > > -- > > 2.30.2 > >
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 847bdba..5eab1ed 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; pmpcfg_shift = (n & 7) << 3; #else - return SBI_ENOTSUPP; +# error "Unexpected __riscv_xlen" #endif pmpaddr_csr = CSR_PMPADDR0 + n; @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; pmpcfg_shift = (n & 7) << 3; #else - return SBI_ENOTSUPP; +# error "Unexpected __riscv_xlen" #endif pmpaddr_csr = CSR_PMPADDR0 + n;
pmp_set/pmp_get calculates the location of the CSR register separately through conditional compilation. In the case of non-32-bit and 64-bit, we can report an error directly through #error without putting it at runtime Signed-off-by: Xiang W <wxjstz@126.com> --- lib/sbi/riscv_asm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)