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Sat, 15 Aug 2020 17:01:36 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH 2/2] lib: sbi: Handle the case were MTVAL has illegal instruction address Date: Sat, 15 Aug 2020 22:30:55 +0530 Message-Id: <20200815170055.286732-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200815170055.286732-1-anup.patel@wdc.com> References: <20200815170055.286732-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR0101CA0064.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:e::26) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (42.109.140.22) by MAXPR0101CA0064.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:e::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3283.16 via Frontend Transport; Sat, 15 Aug 2020 17:01:32 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [42.109.140.22] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 07ed4f3a-7e89-4ff4-e489-08d8413cdeb5 X-MS-TrafficTypeDiagnostic: DM6PR04MB6956: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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To handle above case, we fix sbi_illegal_insn_handler() without any impact on RISC-V v1.10 (or higher) systems. This achieved by exploiting the fact that program counter (and instruction address) is always 2-byte aligned in RISC-V world. Signed-off-by: Anup Patel Tested-by: Heinrich Schuchardt Reviewed-by: Atish Patra Reviewed-by: Bin Meng --- lib/sbi/sbi_illegal_insn.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c index 0e5523f..779a727 100644 --- a/lib/sbi/sbi_illegal_insn.c +++ b/lib/sbi/sbi_illegal_insn.c @@ -118,13 +118,22 @@ int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs) { struct sbi_trap_info uptrap; + /* + * We only deal with 32bit (or longer) illegal instructions. If we + * see instruction is zero OR instruction is 16bit then we fetch and + * check the instruction encoding using unprivilege access. + * + * The program counter (PC) in RISC-V world is always 2-byte aligned + * so handling only 32bit (or longer) illegal instructions also help + * the case where MTVAL CSR contains instruction address for illegal + * instruction trap. + */ + if (unlikely((insn & 3) != 3)) { - if (insn == 0) { - insn = sbi_get_insn(regs->mepc, &uptrap); - if (uptrap.cause) { - uptrap.epc = regs->mepc; - return sbi_trap_redirect(regs, &uptrap); - } + insn = sbi_get_insn(regs->mepc, &uptrap); + if (uptrap.cause) { + uptrap.epc = regs->mepc; + return sbi_trap_redirect(regs, &uptrap); } if ((insn & 3) != 3) return truly_illegal_insn(insn, regs);