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CAT:NONE; SFTY:; SFS:(4636009)(346002)(376002)(39860400002)(396003)(366004)(136003)(66946007)(66556008)(66476007)(6636002)(26005)(8886007)(54906003)(478600001)(110136005)(316002)(8676002)(8936002)(956004)(2616005)(55016002)(7696005)(52116002)(44832011)(5660300002)(86362001)(4326008)(16526019)(186003)(6666004)(2906002)(36756003)(83380400001)(1076003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: eP8AEQMr7kpCEYc4gipY4JnlU74atO6nZFXI9As3hHwSVowdUnuZufiJMO7rtM8Xb9tJzkzEzdMmuz8IpaS3aW7kFJPvw/nzn+tYEbvh82S8U18+1WHX71osDMS4uJRPPvnMiDKuJVqLHJvP22UJz82EvouqbeIcZpFBIpsFXv+ThZo33Xnhz0N0yvqtMyNSq6nBl4b4G/xORSd/s9MqnIc1IK0oziRwETUQK58MeP/dnt+XSsjxS4AJ+cxegUBIoyOl1dMu9xos5BhhK2PC45uz/AlmLhWS6FMDy6UAC66Bhp+e9G8SjDurriyZ5ONXZIzRip0p22f5UdCl0mjwcrEF9c5vEcn4XtronfD0U9fbvhG2o8zMkFdDsL3EOghUMkEm6PrYBiGdZD1baVJdSGXTYMVgciWyEohQejmwe0DZHA6/O4eQ8p+XbHh+PyfQvPyj7nYU/1BpFMIveHKTADDpF5J9aSYpP8Gg2IAKbrcvu42PFcMB2Ya3AkALeILpNXhARKy7q5yLwXG4WmekVZFP/Bbj8rUCand59pOnpnU0rtNhyjtdowsrNv7GNXsNerBrry93VUYVuEi9fJRqnwO7rIaMiY2tL0Ou91CnxXsi/byEIlQ4a36Lzu4Mf6YF9W0mkpsMoqZGY/Ui+ZsO8A== X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9fe1d62-cffc-4e4a-630b-08d83d34b936 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2020 13:53:13.1206 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: i+gO1y25lTj/ics8nVG4fMkDGFJLPPUTEcs1qpG1iMJw6YSCrMkuUBSxB4h/z8f4p2c4f7gJf8h7f39tLmrW+w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4811 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200810_095328_657409_EEE25BD2 X-CRM114-Status: GOOD ( 14.96 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , opensbi@lists.infradead.org Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently, the low-level trap handler (i.e. _trap_handler()) uses branch instructions to conditionally setup exception stack based on which mode trap occured. This patch implements exception stack setup using xor instructions which is 2 instructions less compared to previous approach and faster due to lack of branch instructions. The new exception stack setup approach can be best described by the following pseudocode: Came_From_M_Mode = (MSTATUS.MPP & 0x2) >> 1 Exception_Stack = TP ^ (Came_From_M_Mode * (SP ^ TP)) Came_From_M_Mode = 0 ==> Exception_Stack = TP Came_From_M_Mode = 1 ==> Exception_Stack = SP Signed-off-by: Anup Patel --- firmware/fw_base.S | 49 ++++++++++++++++++++-------------------------- 1 file changed, 21 insertions(+), 28 deletions(-) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index b66ac41..53a9a48 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -490,35 +490,28 @@ _trap_handler: /* Save T0 in scratch space */ REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp) - /* Check which mode we came from */ + /* + * Set T0 to appropriate exception stack + * + * Came_From_M_Mode = (MSTATUS.MPP & 0x2) >> 1 + * Exception_Stack = TP ^ (Came_From_M_Mode * (SP ^ TP)) + * + * Came_From_M_Mode = 0 ==> Exception_Stack = TP + * Came_From_M_Mode = 1 ==> Exception_Stack = SP + */ csrr t0, CSR_MSTATUS - srl t0, t0, MSTATUS_MPP_SHIFT - and t0, t0, PRV_M - xori t0, t0, PRV_M - beq t0, zero, _trap_handler_m_mode - - /* We came from S-mode or U-mode */ -_trap_handler_s_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Setup exception stack */ - add sp, tp, -(SBI_TRAP_REGS_SIZE) - - /* Jump to code common for all modes */ - j _trap_handler_all_mode - - /* We came from M-mode */ -_trap_handler_m_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Re-use current SP as exception stack */ - add sp, sp, -(SBI_TRAP_REGS_SIZE) - -_trap_handler_all_mode: - /* Save original SP (from T0) on stack */ - REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp) + srl t0, t0, (MSTATUS_MPP_SHIFT + 1) + and t0, t0, 0x1 + xor sp, sp, tp + mul t0, t0, sp + xor sp, sp, tp + xor t0, tp, t0 + + /* Save original SP on exception stack */ + REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0) + + /* Set SP to exception stack and make room for trap registers */ + add sp, t0, -(SBI_TRAP_REGS_SIZE) /* Restore T0 from scratch space */ REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)