| Message ID | 20240319093405.39833-5-manojkiran.eda@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add eSPI device driver (flash channel) | expand |
On 19/03/24 3:26 pm, Krzysztof Kozlowski wrote: > On 19/03/2024 10:34, Manojkiran Eda wrote: >> This commit adds the device tree bindings for aspeed eSPI >> controller. >> >> Although aspeed eSPI hardware supports 4 different channels, >> this commit only adds the support for flash channel, the >> bindings for other channels could be upstreamed when the driver >> support for those are added. >> >> Signed-off-by: Manojkiran Eda<manojkiran.eda@gmail.com> >> --- >> .../bindings/soc/aspeed/aspeed,espi.yaml | 94 +++++++++++++++++++ >> 1 file changed, 94 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml >> >> diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml >> new file mode 100644 >> index 000000000000..3d3ad528e3b3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml > Why Rob's comments got ignored? > > This is not a soc component. I did not mean to ignore, i have few reasons listed below that provides information on why i felt this belongs into soc. > >> @@ -0,0 +1,94 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# # Copyright (c) 2024 IBM Corporation. >> +# # Copyright (c) 2021 Aspeed Technology Inc. >> +%YAML 1.2 >> +--- >> +$id:http://devicetree.org/schemas/soc/aspeed/aspeed,espi.yaml# >> +$schema:http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Aspeed eSPI Controller >> + >> +maintainers: >> + - Manojkiran Eda<manojkiran.eda@gmail.com> >> + - Patrick Rudolph<patrick.rudolph@9elements.com> >> + - Chia-Wei Wang<chiawei_wang@aspeedtech.com> >> + - Ryan Chen<ryan_chen@aspeedtech.com> >> + >> +description: >> + Aspeed eSPI controller implements a device side eSPI endpoint device >> + supporting the flash channel. > Explain what is eSPI. eSPI is a serial bus interface for client and server platforms that is based on SPI, using the same master and slave topology but operates with a different protocol to meet new requirements. For instance, eSPI uses I/O, or input/output, communication, instead of MOSI/MISO used in SPI. It also includes a transaction layer on top of the SPI protocol, defining packets such as command and response packets that allow both the master and slave to initiate alert and reset signals. eSPI supports communication between Embedded Controller (EC), Baseboard Management Controller (BMC), Super-I/O (SIO) and Port-80 debug cards. I could add this to the commit message as well in the next patchset. > >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - aspeed,ast2500-espi >> + - aspeed,ast2600-espi >> + - const: simple-mfd > > That's not simple-mfd. You have driver for this. Drop. > >> + - const: syscon > That's not syscon. Why do you have ranges then? Where is any explanation > of hardware which would justify such combination? > >> + >> + reg: >> + maxItems: 1 >> + >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 1 >> + >> + ranges: true >> + >> +patternProperties: >> + "^espi-ctrl@[0-9a-f]+$": >> + type: object >> + >> + description: Controls the flash channel of eSPI hardware > That explains nothing. Unless you wanted to use here MTD bindings. > > This binding did not improve much. I don't understand why this is not > SPI (nothing in commit msg, nothing in description), what is eSPI, eSPI uses Peripheral, Virtual Wire, Out of Band, and Flash Access channels to communicate different sets of data. * The *Peripheral* Channel is used for communication between eSPI host bridge located on the master side and eSPI endpoints located on the slave side. LPC Host and LPC Peripherals are an example of eSPI host bridge and eSPI endpoints respectively. * *Virtual Wire* Channel: The Virtual Wire channel is used to communicate the state of sideband pins or GPIO tunneled through eSPI as in-band messages. Serial IRQ interrupts are communicated through this channel as in-band messages. * *OOB* Channel: The SMBus packets are tunneled through eSPI as Out-Of-Band (OOB) messages. The whole SMBus packet is embedded inside the eSPI OOB message as data. * *Flash Access* Channel: The Flash Access channel provides a path allowing the flash components to be shared run-time between chipset and the eSPI slaves that require flash accesses such as EC (Embedded Controller) and BMC. Although , eSPI reuses the timing and electrical specification of Serial Peripheral Interface (SPI) but it runs an entirely different protocol to meet a set of different requirements. Which is why i felt probably placing this in soc was a better choice rather than spi. Do you think otherwise ? > why > do you need child device, what are other children (commit msg is quite > vague here). Why there is no MTD bindings here? > > All this looks like crafted for your driver, Apologies, this was not my intention. I wanted this to be as generic as possible. But i don't really have much knowledge on what's the right way to model things in kernel at the moment. Still trying to learn and understand by looking at various other drivers. Appreciate all the feedback. > instead of using existing > DT bindings like SPI or MTD/NAND. This is a strong no-go. >> + >> + properties: >> + compatible: >> + items: > No items, just use enum. sure, will fix it. >> + - enum: >> + - aspeed,ast2500-espi-ctrl >> + - aspeed,ast2600-espi-ctrl >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + required: >> + - compatible >> + - interrupts >> + - clocks >> + >> +required: >> + - compatible >> + - reg >> + - "#address-cells" >> + - "#size-cells" >> + - ranges >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/clock/ast2600-clock.h> >> + >> + espi: espi@1e6ee000 { >> + compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon"; >> + reg = <0x1e6ee000 0x1000>; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x1e6ee000 0x1000>; >> + >> + espi_ctrl: espi-ctrl@0 { >> + compatible = "aspeed,ast2600-espi-ctrl"; >> + reg = <0x0 0x800>,<0x0 0x4000000>; > Fix your style in DTS. There is always a space after ','. sure , will fix that. Is there a link that could help me understand various styling requirements on the DTS files. Also is there any formatting tool available currently ? that could fix the styling in the DTS files automatically rather than manual inspection/modification. Did i accidentally missed running some tool check ? > >> + reg-names = "espi_ctrl","espi_flash"; >> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; >> + }; >> + }; > Best regards, > Krzysztof > > Krzysztof,Thanks for the review comments. I am still figuring out few of the review comments (would need a little more time, since its my first attempt into kernel development) , but mean while I wanted to make sure if the direction of choosing "soc" vs "spi" was correct, so that i could re-work on the comments.So i have selectively answered to few of your comments. Could you let me know if the reasoning that was provided in reply to your comments help ? Thanks, Manoj
On Wed, Mar 20, 2024 at 03:29:15PM +0530, Manojkiran Eda wrote: > On 19/03/24 3:26 pm, Krzysztof Kozlowski wrote: > > On 19/03/2024 10:34, Manojkiran Eda wrote: > > This commit adds the device tree bindings for aspeed eSPI > controller. > > Although aspeed eSPI hardware supports 4 different channels, > this commit only adds the support for flash channel, the > bindings for other channels could be upstreamed when the driver > support for those are added. > > Signed-off-by: Manojkiran Eda [1]<manojkiran.eda@gmail.com> > --- > .../bindings/soc/aspeed/aspeed,espi.yaml | 94 +++++++++++++++++++ > 1 file changed, 94 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yam > l > > diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml b/Doc > umentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml > new file mode 100644 > index 000000000000..3d3ad528e3b3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml > > Why Rob's comments got ignored? > > This is not a soc component. > > I did not mean to ignore, i have few reasons listed below that provides > information on why i felt this belongs into soc. Fix you email program to not send multi-part (txt plus html) emails. Plain text only on maillists. Rob
On 20/03/24 8:14 pm, Krzysztof Kozlowski wrote: > On 20/03/2024 10:59, Manojkiran Eda wrote: >> >> On 19/03/24 3:26 pm, Krzysztof Kozlowski wrote: >>> On 19/03/2024 10:34, Manojkiran Eda wrote: >>>> This commit adds the device tree bindings for aspeed eSPI >>>> controller. >>>> >>>> Although aspeed eSPI hardware supports 4 different channels, >>>> this commit only adds the support for flash channel, the >>>> bindings for other channels could be upstreamed when the driver >>>> support for those are added. >>>> >>>> Signed-off-by: Manojkiran Eda<manojkiran.eda@gmail.com> >>>> --- >>>> .../bindings/soc/aspeed/aspeed,espi.yaml | 94 +++++++++++++++++++ >>>> 1 file changed, 94 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml >>>> new file mode 100644 >>>> index 000000000000..3d3ad528e3b3 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml >>> Why Rob's comments got ignored? >>> >>> This is not a soc component. >> I did not mean to ignore, i have few reasons listed below that provides >> information on why i felt this belongs into soc. > > soc is dumping ground of things which are purely SoC specific, not > covered by existing hardware structure in bindings. Maybe indeed this > does not have any other place, but did you actually look? > Yes, i did look at existing hardware bindings, and cannot seem to find out any other suitable place. I can definitely look again. > Anyway, please CC SPI maintainers on future submission. Sure, will add them. > >>> >>>> @@ -0,0 +1,94 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +# # Copyright (c) 2024 IBM Corporation. >>>> +# # Copyright (c) 2021 Aspeed Technology Inc. >>>> +%YAML 1.2 >>>> +--- >>>> +$id:http://devicetree.org/schemas/soc/aspeed/aspeed,espi.yaml# >>>> +$schema:http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Aspeed eSPI Controller >>>> + >>>> +maintainers: >>>> + - Manojkiran Eda<manojkiran.eda@gmail.com> >>>> + - Patrick Rudolph<patrick.rudolph@9elements.com> >>>> + - Chia-Wei Wang<chiawei_wang@aspeedtech.com> >>>> + - Ryan Chen<ryan_chen@aspeedtech.com> >>>> + >>>> +description: >>>> + Aspeed eSPI controller implements a device side eSPI endpoint device >>>> + supporting the flash channel. >>> Explain what is eSPI. >> eSPI is a serial bus interface for client and server platforms that is > > Explain in description of the hardware. Sure, i will add this description in the binding document in the future submission. > >> based on SPI, using the same master and slave topology but operates >> with a different protocol to meet new requirements. For instance, eSPI >> uses I/O, or input/output, communication, instead of MOSI/MISO used in >> SPI. It also includes a transaction layer on top of the SPI protocol, >> defining packets such as command and response packets that allow both >> the master and slave to initiate alert and reset signals. eSPI supports >> communication between Embedded Controller (EC), Baseboard Management >> Controller (BMC), Super-I/O (SIO) and Port-80 debug cards. I could add >> this to the commit message as well in the next patchset. >>> >>>> + >>>> +properties: >>>> + compatible: >>>> + items: >>>> + - enum: >>>> + - aspeed,ast2500-espi >>>> + - aspeed,ast2600-espi >>>> + - const: simple-mfd >>> >>> That's not simple-mfd. You have driver for this. Drop. >>> >>>> + - const: syscon >>> That's not syscon. Why do you have ranges then? Where is any explanation >>> of hardware which would justify such combination? >>> >>>> + >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + "#address-cells": >>>> + const: 1 >>>> + >>>> + "#size-cells": >>>> + const: 1 >>>> + >>>> + ranges: true >>>> + >>>> +patternProperties: >>>> + "^espi-ctrl@[0-9a-f]+$": >>>> + type: object >>>> + >>>> + description: Controls the flash channel of eSPI hardware >>> That explains nothing. Unless you wanted to use here MTD bindings. >>> >>> This binding did not improve much. I don't understand why this is not >>> SPI (nothing in commit msg, nothing in description), what is eSPI, >> >> eSPI uses Peripheral, Virtual Wire, Out of Band, and Flash Access >> channels to communicate different sets of data. > > And what are these channels? What does it mean a "channel"? Is it just > how you organize transfers and classes of devices? Or some sort of > addressable instance on the bus? > Yes, an espi channel provides a means to allow multiple independent flows of traffic to share the same physical bus. Each of the channels has its own dedicated resources such as queue and flow control. > The channels feel like some sort of software or logical concept, not > physical. Physical would be endpoint with peripheral. Or flash memory. A channel is a logical communication pathway or interface between the chipset and peripheral devices. The concept of channels in the ESPI protocol helps organize and manage different types of communication between the chipset and peripherals. Each channel may have its own set of protocols, data transfer rates, and supported features, tailored to the requirements of the devices it serves. > How do they fit here? I am not sure I understand, can you please elaborate ? >> >> * The *Peripheral* Channel is used for communication between eSPI host >> bridge located on the master side and eSPI endpoints located on the >> slave side. LPC Host and LPC Peripherals are an example of eSPI host >> bridge and eSPI endpoints respectively. >> * *Virtual Wire* Channel: The Virtual Wire channel is used to >> communicate the state of sideband pins or GPIO tunneled through eSPI >> as in-band messages. Serial IRQ interrupts are communicated through >> this channel as in-band messages. >> * *OOB* Channel: The SMBus packets are tunneled through eSPI as >> Out-Of-Band (OOB) messages. The whole SMBus packet is embedded >> inside the eSPI OOB message as data. >> * *Flash Access* Channel: The Flash Access channel provides a path >> allowing the flash components to be shared run-time between chipset >> and the eSPI slaves that require flash accesses such as EC (Embedded >> Controller) and BMC. > > Please make binding complete, so define all of the channels. I would like to inquire about the rationale behind this request. Based on previous feedback received from the upstream efforts [https://lore.kernel.org/openbmc/HK0PR06MB37798462D17443C697433D7191D09@HK0PR06MB3779.apcprd06.prod.outlook.com/], suggestions were made to model the flash channel by utilizing the mtd subsystem, the virtual wire channel by utilizing the GPIO subsystem, and to consider the OOB channel as a type of i2c device, thereby allowing it to be utilized by the existing in-kernel MCTP subsystem, among others. My intention was to prioritize upstreaming the flash channel binding, along with its driver code, before proceeding to address other channels. I am curious to understand if it is a strict requirement to have the complete binding upstreamed before addressing the device drivers code. > >> >> Although , eSPI reuses the timing and electrical specification of Serial >> Peripheral Interface (SPI) but it runs an entirely different protocol to >> meet a set of different requirements. Which is why i felt probably >> placing this in soc was a better choice rather than spi. Do you think >> otherwise ? > > soc is dumping ground for things do not fit other places. Are there any > other buses / IP blocks similar to this one? > > > Best regards, > Krzysztof > Thanks, Manoj
diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml new file mode 100644 index 000000000000..3d3ad528e3b3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2024 IBM Corporation. +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/aspeed/aspeed,espi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed eSPI Controller + +maintainers: + - Manojkiran Eda <manojkiran.eda@gmail.com> + - Patrick Rudolph <patrick.rudolph@9elements.com> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + - Ryan Chen <ryan_chen@aspeedtech.com> + +description: + Aspeed eSPI controller implements a device side eSPI endpoint device + supporting the flash channel. + +properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi + - aspeed,ast2600-espi + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^espi-ctrl@[0-9a-f]+$": + type: object + + description: Controls the flash channel of eSPI hardware + + properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi-ctrl + - aspeed,ast2600-espi-ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - interrupts + - clocks + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + espi: espi@1e6ee000 { + compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon"; + reg = <0x1e6ee000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6ee000 0x1000>; + + espi_ctrl: espi-ctrl@0 { + compatible = "aspeed,ast2600-espi-ctrl"; + reg = <0x0 0x800>,<0x0 0x4000000>; + reg-names = "espi_ctrl","espi_flash"; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; + }; + };
This commit adds the device tree bindings for aspeed eSPI controller. Although aspeed eSPI hardware supports 4 different channels, this commit only adds the support for flash channel, the bindings for other channels could be upstreamed when the driver support for those are added. Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com> --- .../bindings/soc/aspeed/aspeed,espi.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,espi.yaml